Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4248913 |
1 |
|
|
T23 |
257 |
|
T24 |
449 |
|
T25 |
392 |
| auto[1] |
2049061 |
1 |
|
|
T28 |
147 |
|
T29 |
1548 |
|
T31 |
39 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6032612 |
1 |
|
|
T23 |
257 |
|
T24 |
449 |
|
T25 |
392 |
| auto[1] |
265362 |
1 |
|
|
T28 |
12 |
|
T29 |
303 |
|
T31 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4252543 |
1 |
|
|
T23 |
257 |
|
T24 |
449 |
|
T25 |
392 |
| auto[1] |
2045431 |
1 |
|
|
T28 |
136 |
|
T29 |
1505 |
|
T31 |
45 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
892965 |
1 |
|
|
T28 |
51 |
|
T29 |
533 |
|
T31 |
24 |
| auto[1] |
auto[0] |
auto[1] |
133417 |
1 |
|
|
T28 |
5 |
|
T29 |
136 |
|
T31 |
1 |
| auto[1] |
auto[1] |
auto[0] |
887104 |
1 |
|
|
T28 |
73 |
|
T29 |
669 |
|
T31 |
18 |
| auto[1] |
auto[1] |
auto[1] |
131945 |
1 |
|
|
T28 |
7 |
|
T29 |
167 |
|
T31 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |