Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4247372 |
1 |
|
|
T23 |
257 |
|
T24 |
449 |
|
T25 |
392 |
| auto[1] |
2050602 |
1 |
|
|
T28 |
120 |
|
T29 |
1696 |
|
T31 |
10 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5288001 |
1 |
|
|
T23 |
257 |
|
T24 |
449 |
|
T25 |
392 |
| auto[1] |
1009973 |
1 |
|
|
T28 |
50 |
|
T29 |
764 |
|
T31 |
12 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4250248 |
1 |
|
|
T23 |
257 |
|
T24 |
449 |
|
T25 |
392 |
| auto[1] |
2047726 |
1 |
|
|
T28 |
122 |
|
T29 |
1568 |
|
T31 |
27 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
518848 |
1 |
|
|
T28 |
32 |
|
T29 |
322 |
|
T31 |
15 |
| auto[1] |
auto[0] |
auto[1] |
506310 |
1 |
|
|
T28 |
26 |
|
T29 |
348 |
|
T31 |
9 |
| auto[1] |
auto[1] |
auto[0] |
518905 |
1 |
|
|
T28 |
40 |
|
T29 |
482 |
|
T57 |
63 |
| auto[1] |
auto[1] |
auto[1] |
503663 |
1 |
|
|
T28 |
24 |
|
T29 |
416 |
|
T31 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |