Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	1590952	1			T24	1		T25	1		T26	1
all_pins[1]	1590952	1			T24	1		T25	1		T26	1
all_pins[2]	1590952	1			T24	1		T25	1		T26	1
all_pins[3]	1590952	1			T24	1		T25	1		T26	1
all_pins[4]	1590952	1			T24	1		T25	1		T26	1
all_pins[5]	1590952	1			T24	1		T25	1		T26	1
all_pins[6]	1590952	1			T24	1		T25	1		T26	1
all_pins[7]	1590952	1			T24	1		T25	1		T26	1
all_pins[8]	1590952	1			T24	1		T25	1		T26	1
all_pins[9]	1590952	1			T24	1		T25	1		T26	1
all_pins[10]	1590952	1			T24	1		T25	1		T26	1
all_pins[11]	1590952	1			T24	1		T25	1		T26	1
all_pins[12]	1590952	1			T24	1		T25	1		T26	1
all_pins[13]	1590952	1			T24	1		T25	1		T26	1
all_pins[14]	1590952	1			T24	1		T25	1		T26	1
all_pins[15]	1590952	1			T24	1		T25	1		T26	1
all_pins[16]	1590952	1			T24	1		T25	1		T26	1
all_pins[17]	1590952	1			T24	1		T25	1		T26	1
all_pins[18]	1590952	1			T24	1		T25	1		T26	1
all_pins[19]	1590952	1			T24	1		T25	1		T26	1
all_pins[20]	1590952	1			T24	1		T25	1		T26	1
all_pins[21]	1590952	1			T24	1		T25	1		T26	1
all_pins[22]	1590952	1			T24	1		T25	1		T26	1
all_pins[23]	1590952	1			T24	1		T25	1		T26	1
all_pins[24]	1590952	1			T24	1		T25	1		T26	1
all_pins[25]	1590952	1			T24	1		T25	1		T26	1
all_pins[26]	1590952	1			T24	1		T25	1		T26	1
all_pins[27]	1590952	1			T24	1		T25	1		T26	1
all_pins[28]	1590952	1			T24	1		T25	1		T26	1
all_pins[29]	1590952	1			T24	1		T25	1		T26	1
all_pins[30]	1590952	1			T24	1		T25	1		T26	1
all_pins[31]	1590952	1			T24	1		T25	1		T26	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	31654431	1			T24	32		T25	32		T26	32
values[0x1]	19256033	1			T30	1807		T33	296		T34	489
transitions[0x0=>0x1]	11539136	1			T30	1144		T33	217		T34	313
transitions[0x1=>0x0]	11538975	1			T30	1143		T33	217		T34	313

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	989567	1			T24	1		T25	1		T26	1
all_pins[0]	values[0x1]	601385	1			T30	58		T33	15		T34	14
all_pins[0]	transitions[0x0=>0x1]	373556	1			T30	25		T33	14		T34	9
all_pins[0]	transitions[0x1=>0x0]	371240	1			T30	47		T33	7		T34	11
all_pins[1]	values[0x0]	989395	1			T24	1		T25	1		T26	1
all_pins[1]	values[0x1]	601557	1			T30	66		T33	13		T34	25
all_pins[1]	transitions[0x0=>0x1]	358220	1			T30	42		T33	6		T34	18
all_pins[1]	transitions[0x1=>0x0]	358048	1			T30	34		T33	8		T34	7
all_pins[2]	values[0x0]	986430	1			T24	1		T25	1		T26	1
all_pins[2]	values[0x1]	604522	1			T30	42		T33	13		T34	15
all_pins[2]	transitions[0x0=>0x1]	362074	1			T30	16		T33	9		T34	5
all_pins[2]	transitions[0x1=>0x0]	359109	1			T30	40		T33	9		T34	15
all_pins[3]	values[0x0]	990569	1			T24	1		T25	1		T26	1
all_pins[3]	values[0x1]	600383	1			T30	88		T33	4		T34	18
all_pins[3]	transitions[0x0=>0x1]	357514	1			T30	64		T34	11		T62	29
all_pins[3]	transitions[0x1=>0x0]	361653	1			T30	18		T33	9		T34	8
all_pins[4]	values[0x0]	989823	1			T24	1		T25	1		T26	1
all_pins[4]	values[0x1]	601129	1			T30	44		T34	5		T62	38
all_pins[4]	transitions[0x0=>0x1]	360306	1			T30	28		T34	4		T62	32
all_pins[4]	transitions[0x1=>0x0]	359560	1			T30	72		T33	4		T34	17
all_pins[5]	values[0x0]	989777	1			T24	1		T25	1		T26	1
all_pins[5]	values[0x1]	601175	1			T30	54		T33	14		T34	7
all_pins[5]	transitions[0x0=>0x1]	360044	1			T30	32		T33	14		T34	7
all_pins[5]	transitions[0x1=>0x0]	359998	1			T30	22		T34	5		T62	17
all_pins[6]	values[0x0]	988617	1			T24	1		T25	1		T26	1
all_pins[6]	values[0x1]	602335	1			T30	41		T33	15		T34	13
all_pins[6]	transitions[0x0=>0x1]	360647	1			T30	29		T33	7		T34	12
all_pins[6]	transitions[0x1=>0x0]	359487	1			T30	42		T33	6		T34	6
all_pins[7]	values[0x0]	989304	1			T24	1		T25	1		T26	1
all_pins[7]	values[0x1]	601648	1			T30	59		T33	5		T34	12
all_pins[7]	transitions[0x0=>0x1]	358161	1			T30	45		T33	2		T34	8
all_pins[7]	transitions[0x1=>0x0]	358848	1			T30	27		T33	12		T34	9
all_pins[8]	values[0x0]	990832	1			T24	1		T25	1		T26	1
all_pins[8]	values[0x1]	600120	1			T30	70		T34	7		T62	69
all_pins[8]	transitions[0x0=>0x1]	360417	1			T30	42		T34	5		T62	41
all_pins[8]	transitions[0x1=>0x0]	361945	1			T30	31		T33	5		T34	10
all_pins[9]	values[0x0]	990151	1			T24	1		T25	1		T26	1
all_pins[9]	values[0x1]	600801	1			T30	58		T33	11		T34	9
all_pins[9]	transitions[0x0=>0x1]	360030	1			T30	29		T33	11		T34	7
all_pins[9]	transitions[0x1=>0x0]	359349	1			T30	41		T34	5		T62	42
all_pins[10]	values[0x0]	988884	1			T24	1		T25	1		T26	1
all_pins[10]	values[0x1]	602068	1			T30	66		T33	9		T34	17
all_pins[10]	transitions[0x0=>0x1]	360917	1			T30	39		T33	9		T34	14
all_pins[10]	transitions[0x1=>0x0]	359650	1			T30	31		T33	11		T34	6
all_pins[11]	values[0x0]	993307	1			T24	1		T25	1		T26	1
all_pins[11]	values[0x1]	597645	1			T30	61		T33	4		T34	6
all_pins[11]	transitions[0x0=>0x1]	358425	1			T30	36		T33	1		T34	3
all_pins[11]	transitions[0x1=>0x0]	362848	1			T30	41		T33	6		T34	14
all_pins[12]	values[0x0]	986291	1			T24	1		T25	1		T26	1
all_pins[12]	values[0x1]	604661	1			T30	56		T33	5		T34	24
all_pins[12]	transitions[0x0=>0x1]	364216	1			T30	33		T33	5		T34	20
all_pins[12]	transitions[0x1=>0x0]	357200	1			T30	38		T33	4		T34	2
all_pins[13]	values[0x0]	991979	1			T24	1		T25	1		T26	1
all_pins[13]	values[0x1]	598973	1			T30	72		T33	6		T34	23
all_pins[13]	transitions[0x0=>0x1]	357933	1			T30	55		T33	3		T34	7
all_pins[13]	transitions[0x1=>0x0]	363621	1			T30	39		T33	2		T34	8
all_pins[14]	values[0x0]	986901	1			T24	1		T25	1		T26	1
all_pins[14]	values[0x1]	604051	1			T30	53		T33	2		T34	16
all_pins[14]	transitions[0x0=>0x1]	364587	1			T30	35		T33	2		T34	8
all_pins[14]	transitions[0x1=>0x0]	359509	1			T30	54		T33	6		T34	15
all_pins[15]	values[0x0]	987961	1			T24	1		T25	1		T26	1
all_pins[15]	values[0x1]	602991	1			T30	60		T33	9		T34	13
all_pins[15]	transitions[0x0=>0x1]	359953	1			T30	30		T33	9		T34	5
all_pins[15]	transitions[0x1=>0x0]	361013	1			T30	23		T33	2		T34	8
all_pins[16]	values[0x0]	988325	1			T24	1		T25	1		T26	1
all_pins[16]	values[0x1]	602627	1			T30	44		T33	22		T34	10
all_pins[16]	transitions[0x0=>0x1]	360512	1			T30	29		T33	13		T34	9
all_pins[16]	transitions[0x1=>0x0]	360876	1			T30	45		T34	12		T62	19
all_pins[17]	values[0x0]	993829	1			T24	1		T25	1		T26	1
all_pins[17]	values[0x1]	597123	1			T30	24		T34	21		T62	68
all_pins[17]	transitions[0x0=>0x1]	356671	1			T30	23		T34	18		T62	54
all_pins[17]	transitions[0x1=>0x0]	362175	1			T30	43		T33	22		T34	7
all_pins[18]	values[0x0]	988651	1			T24	1		T25	1		T26	1
all_pins[18]	values[0x1]	602301	1			T30	51		T33	15		T34	17
all_pins[18]	transitions[0x0=>0x1]	361654	1			T30	48		T33	15		T34	6
all_pins[18]	transitions[0x1=>0x0]	356476	1			T30	21		T34	10		T62	56
all_pins[19]	values[0x0]	990918	1			T24	1		T25	1		T26	1
all_pins[19]	values[0x1]	600034	1			T30	34		T33	25		T34	14
all_pins[19]	transitions[0x0=>0x1]	357873	1			T30	15		T33	13		T34	11
all_pins[19]	transitions[0x1=>0x0]	360140	1			T30	32		T33	3		T34	14
all_pins[20]	values[0x0]	990503	1			T24	1		T25	1		T26	1
all_pins[20]	values[0x1]	600449	1			T30	30		T33	11		T34	22
all_pins[20]	transitions[0x0=>0x1]	359927	1			T30	22		T33	3		T34	20
all_pins[20]	transitions[0x1=>0x0]	359512	1			T30	26		T33	17		T34	12
all_pins[21]	values[0x0]	987446	1			T24	1		T25	1		T26	1
all_pins[21]	values[0x1]	603506	1			T30	72		T33	3		T34	13
all_pins[21]	transitions[0x0=>0x1]	361774	1			T30	63		T34	8		T62	14
all_pins[21]	transitions[0x1=>0x0]	358717	1			T30	21		T33	8		T34	17
all_pins[22]	values[0x0]	984267	1			T24	1		T25	1		T26	1
all_pins[22]	values[0x1]	606685	1			T30	55		T34	23		T62	51
all_pins[22]	transitions[0x0=>0x1]	364592	1			T30	27		T34	18		T62	40
all_pins[22]	transitions[0x1=>0x0]	361413	1			T30	44		T33	3		T34	8
all_pins[23]	values[0x0]	987331	1			T24	1		T25	1		T26	1
all_pins[23]	values[0x1]	603621	1			T30	67		T33	4		T34	17
all_pins[23]	transitions[0x0=>0x1]	359756	1			T30	43		T33	4		T34	7
all_pins[23]	transitions[0x1=>0x0]	362820	1			T30	31		T34	13		T62	23
all_pins[24]	values[0x0]	987365	1			T24	1		T25	1		T26	1
all_pins[24]	values[0x1]	603587	1			T30	67		T33	11		T34	9
all_pins[24]	transitions[0x0=>0x1]	360004	1			T30	35		T33	11		T34	5
all_pins[24]	transitions[0x1=>0x0]	360038	1			T30	35		T33	4		T34	13
all_pins[25]	values[0x0]	987501	1			T24	1		T25	1		T26	1
all_pins[25]	values[0x1]	603451	1			T30	69		T33	19		T34	14
all_pins[25]	transitions[0x0=>0x1]	361165	1			T30	30		T33	19		T34	8
all_pins[25]	transitions[0x1=>0x0]	361301	1			T30	28		T33	11		T34	3
all_pins[26]	values[0x0]	992735	1			T24	1		T25	1		T26	1
all_pins[26]	values[0x1]	598217	1			T30	43		T33	12		T34	18
all_pins[26]	transitions[0x0=>0x1]	357170	1			T30	33		T33	6		T34	8
all_pins[26]	transitions[0x1=>0x0]	362404	1			T30	59		T33	13		T34	4
all_pins[27]	values[0x0]	988792	1			T24	1		T25	1		T26	1
all_pins[27]	values[0x1]	602160	1			T30	57		T33	6		T34	22
all_pins[27]	transitions[0x0=>0x1]	361207	1			T30	41		T33	5		T34	16
all_pins[27]	transitions[0x1=>0x0]	357264	1			T30	27		T33	11		T34	12
all_pins[28]	values[0x0]	986893	1			T24	1		T25	1		T26	1
all_pins[28]	values[0x1]	604059	1			T30	61		T33	20		T34	12
all_pins[28]	transitions[0x0=>0x1]	360923	1			T30	31		T33	19		T34	7
all_pins[28]	transitions[0x1=>0x0]	359024	1			T30	27		T33	5		T34	17
all_pins[29]	values[0x0]	988494	1			T24	1		T25	1		T26	1
all_pins[29]	values[0x1]	602458	1			T30	32		T33	7		T34	17
all_pins[29]	transitions[0x0=>0x1]	359395	1			T30	24		T33	7		T34	8
all_pins[29]	transitions[0x1=>0x0]	360996	1			T30	53		T33	20		T34	3
all_pins[30]	values[0x0]	989871	1			T24	1		T25	1		T26	1
all_pins[30]	values[0x1]	601081	1			T30	72		T33	8		T34	20
all_pins[30]	transitions[0x0=>0x1]	359876	1			T30	59		T33	6		T34	10
all_pins[30]	transitions[0x1=>0x0]	361253	1			T30	19		T33	5		T34	7
all_pins[31]	values[0x0]	991722	1			T24	1		T25	1		T26	1
all_pins[31]	values[0x1]	599230	1			T30	81		T33	8		T34	16
all_pins[31]	transitions[0x0=>0x1]	359637	1			T30	41		T33	4		T34	11
all_pins[31]	transitions[0x1=>0x0]	361488	1			T30	32		T33	4		T34	15