Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	6476306	1			T24	122		T25	156		T26	398
all_values[1]	6476306	1			T24	122		T25	156		T26	398
all_values[2]	6476306	1			T24	122		T25	156		T26	398
all_values[3]	6476306	1			T24	122		T25	156		T26	398
all_values[4]	6476306	1			T24	122		T25	156		T26	398
all_values[5]	6476306	1			T24	122		T25	156		T26	398
all_values[6]	6476306	1			T24	122		T25	156		T26	398
all_values[7]	6476306	1			T24	122		T25	156		T26	398
all_values[8]	6476306	1			T24	122		T25	156		T26	398
all_values[9]	6476306	1			T24	122		T25	156		T26	398
all_values[10]	6476306	1			T24	122		T25	156		T26	398
all_values[11]	6476306	1			T24	122		T25	156		T26	398
all_values[12]	6476306	1			T24	122		T25	156		T26	398
all_values[13]	6476306	1			T24	122		T25	156		T26	398
all_values[14]	6476306	1			T24	122		T25	156		T26	398
all_values[15]	6476306	1			T24	122		T25	156		T26	398
all_values[16]	6476306	1			T24	122		T25	156		T26	398
all_values[17]	6476306	1			T24	122		T25	156		T26	398
all_values[18]	6476306	1			T24	122		T25	156		T26	398
all_values[19]	6476306	1			T24	122		T25	156		T26	398
all_values[20]	6476306	1			T24	122		T25	156		T26	398
all_values[21]	6476306	1			T24	122		T25	156		T26	398
all_values[22]	6476306	1			T24	122		T25	156		T26	398
all_values[23]	6476306	1			T24	122		T25	156		T26	398
all_values[24]	6476306	1			T24	122		T25	156		T26	398
all_values[25]	6476306	1			T24	122		T25	156		T26	398
all_values[26]	6476306	1			T24	122		T25	156		T26	398
all_values[27]	6476306	1			T24	122		T25	156		T26	398
all_values[28]	6476306	1			T24	122		T25	156		T26	398
all_values[29]	6476306	1			T24	122		T25	156		T26	398
all_values[30]	6476306	1			T24	122		T25	156		T26	398
all_values[31]	6476306	1			T24	122		T25	156		T26	398

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

137820406

1

T24

3904

T25

4992

T26

12736

auto[1]

69421386

1

T30

3822

T33

878

T34

1062

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

81966241

1

T24

3904

T25

4992

T26

12736

auto[1]

125275551

1

T30

5832

T33

1374

T34

1451

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

205359691

1

T24

3904

T25

4992

T26

12736

auto[1]

1882101

1

T33

158

T34

118

T1

1661

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	2340694	1			T24	122		T25	156		T26	398
all_values[0]	auto[0]	auto[0]	auto[1]	1939539	1			T30	100		T33	33		T34	27
all_values[0]	auto[0]	auto[1]	auto[0]	215115	1			T30	14		T33	5		T62	29
all_values[0]	auto[0]	auto[1]	auto[1]	1922004	1			T30	100		T33	25		T34	17
all_values[0]	auto[1]	auto[0]	auto[1]	29850	1			T33	3		T34	3		T1	38
all_values[0]	auto[1]	auto[1]	auto[1]	29104	1			T33	2		T34	1		T1	11
all_values[1]	auto[0]	auto[0]	auto[0]	2339342	1			T24	122		T25	156		T26	398
all_values[1]	auto[0]	auto[0]	auto[1]	1919550	1			T30	78		T33	7		T34	21
all_values[1]	auto[0]	auto[1]	auto[0]	218196	1			T30	20		T33	19		T34	3
all_values[1]	auto[0]	auto[1]	auto[1]	1940384	1			T30	107		T33	18		T34	38
all_values[1]	auto[1]	auto[0]	auto[1]	29580	1			T33	4		T34	4		T1	24
all_values[1]	auto[1]	auto[1]	auto[1]	29254	1			T33	3		T1	18		T13	3
all_values[2]	auto[0]	auto[0]	auto[0]	2341908	1			T24	122		T25	156		T26	398
all_values[2]	auto[0]	auto[0]	auto[1]	1923909	1			T30	106		T33	23		T34	11
all_values[2]	auto[0]	auto[1]	auto[0]	216496	1			T30	32		T33	15		T34	7
all_values[2]	auto[0]	auto[1]	auto[1]	1935282	1			T30	75		T33	21		T34	22
all_values[2]	auto[1]	auto[0]	auto[1]	29438	1			T33	4		T34	1		T1	28
all_values[2]	auto[1]	auto[1]	auto[1]	29273	1			T34	2		T1	34		T13	1
all_values[3]	auto[0]	auto[0]	auto[0]	2341822	1			T24	122		T25	156		T26	398
all_values[3]	auto[0]	auto[0]	auto[1]	1950040	1			T30	65		T33	36		T34	24
all_values[3]	auto[0]	auto[1]	auto[0]	213700	1			T30	34		T33	2		T34	7
all_values[3]	auto[0]	auto[1]	auto[1]	1911945	1			T30	123		T33	4		T34	23
all_values[3]	auto[1]	auto[0]	auto[1]	29696	1			T33	5		T34	2		T1	34
all_values[3]	auto[1]	auto[1]	auto[1]	29103	1			T33	1		T34	2		T1	12
all_values[4]	auto[0]	auto[0]	auto[0]	2345151	1			T24	122		T25	156		T26	398
all_values[4]	auto[0]	auto[0]	auto[1]	1941110	1			T30	121		T33	44		T34	40
all_values[4]	auto[0]	auto[1]	auto[0]	218959	1			T30	23		T33	12		T34	9
all_values[4]	auto[0]	auto[1]	auto[1]	1912376	1			T30	74		T34	6		T62	71
all_values[4]	auto[1]	auto[0]	auto[1]	29396	1			T33	5		T34	4		T1	32
all_values[4]	auto[1]	auto[1]	auto[1]	29314	1			T34	1		T1	21		T13	3
all_values[5]	auto[0]	auto[0]	auto[0]	2342706	1			T24	122		T25	156		T26	398
all_values[5]	auto[0]	auto[0]	auto[1]	1932583	1			T30	87		T33	14		T34	29
all_values[5]	auto[0]	auto[1]	auto[0]	218534	1			T30	23		T33	22		T34	19
all_values[5]	auto[0]	auto[1]	auto[1]	1923574	1			T30	95		T33	16		T34	6
all_values[5]	auto[1]	auto[0]	auto[1]	30015	1			T33	5		T34	3		T1	31
all_values[5]	auto[1]	auto[1]	auto[1]	28894	1			T33	2		T1	17		T13	3
all_values[6]	auto[0]	auto[0]	auto[0]	2344434	1			T24	122		T25	156		T26	398
all_values[6]	auto[0]	auto[0]	auto[1]	1929448	1			T30	60		T33	21		T34	13
all_values[6]	auto[0]	auto[1]	auto[0]	219393	1			T30	66		T33	16		T34	9
all_values[6]	auto[0]	auto[1]	auto[1]	1924037	1			T30	72		T33	17		T34	19
all_values[6]	auto[1]	auto[0]	auto[1]	29833	1			T33	3		T34	2		T1	26
all_values[6]	auto[1]	auto[1]	auto[1]	29161	1			T33	3		T34	1		T1	23
all_values[7]	auto[0]	auto[0]	auto[0]	2343386	1			T24	122		T25	156		T26	398
all_values[7]	auto[0]	auto[0]	auto[1]	1934691	1			T30	99		T33	20		T34	19
all_values[7]	auto[0]	auto[1]	auto[0]	218775	1			T30	31		T33	18		T34	13
all_values[7]	auto[0]	auto[1]	auto[1]	1920547	1			T30	91		T33	3		T34	15
all_values[7]	auto[1]	auto[0]	auto[1]	29615	1			T33	1		T34	4		T1	29
all_values[7]	auto[1]	auto[1]	auto[1]	29292	1			T33	1		T34	1		T1	19
all_values[8]	auto[0]	auto[0]	auto[0]	2340387	1			T24	122		T25	156		T26	398
all_values[8]	auto[0]	auto[0]	auto[1]	1936898	1			T30	76		T33	22		T34	39
all_values[8]	auto[0]	auto[1]	auto[0]	219442	1			T30	20		T33	32		T34	7
all_values[8]	auto[0]	auto[1]	auto[1]	1921051	1			T30	121		T34	14		T62	103
all_values[8]	auto[1]	auto[0]	auto[1]	29415	1			T33	1		T34	4		T1	28
all_values[8]	auto[1]	auto[1]	auto[1]	29113	1			T1	19		T13	5		T17	30
all_values[9]	auto[0]	auto[0]	auto[0]	2344552	1			T24	122		T25	156		T26	398
all_values[9]	auto[0]	auto[0]	auto[1]	1929625	1			T30	83		T33	28		T34	28
all_values[9]	auto[0]	auto[1]	auto[0]	218710	1			T30	25		T33	15		T34	23
all_values[9]	auto[0]	auto[1]	auto[1]	1924595	1			T30	103		T33	13		T34	12
all_values[9]	auto[1]	auto[0]	auto[1]	29694	1			T33	6		T34	3		T1	30
all_values[9]	auto[1]	auto[1]	auto[1]	29130	1			T33	1		T1	26		T13	4
all_values[10]	auto[0]	auto[0]	auto[0]	2340569	1			T24	122		T25	156		T26	398
all_values[10]	auto[0]	auto[0]	auto[1]	1932848	1			T30	95		T33	21		T34	14
all_values[10]	auto[0]	auto[1]	auto[0]	219242	1			T30	6		T33	13		T34	7
all_values[10]	auto[0]	auto[1]	auto[1]	1924829	1			T30	113		T33	11		T34	23
all_values[10]	auto[1]	auto[0]	auto[1]	29603	1			T33	5		T34	1		T1	22
all_values[10]	auto[1]	auto[1]	auto[1]	29215	1			T33	1		T34	2		T1	29
all_values[11]	auto[0]	auto[0]	auto[0]	2344980	1			T24	122		T25	156		T26	398
all_values[11]	auto[0]	auto[0]	auto[1]	1927042	1			T30	76		T33	27		T34	2
all_values[11]	auto[0]	auto[1]	auto[0]	220312	1			T30	18		T33	11		T34	32
all_values[11]	auto[0]	auto[1]	auto[1]	1925192	1			T30	102		T33	2		T34	5
all_values[11]	auto[1]	auto[0]	auto[1]	29508	1			T33	4		T34	1		T1	36
all_values[11]	auto[1]	auto[1]	auto[1]	29272	1			T33	1		T34	3		T1	13
all_values[12]	auto[0]	auto[0]	auto[0]	2347015	1			T24	122		T25	156		T26	398
all_values[12]	auto[0]	auto[0]	auto[1]	1927342	1			T30	70		T33	27		T34	25
all_values[12]	auto[0]	auto[1]	auto[0]	224355	1			T30	33		T33	15		T34	7
all_values[12]	auto[0]	auto[1]	auto[1]	1918426	1			T30	90		T33	9		T34	30
all_values[12]	auto[1]	auto[0]	auto[1]	29598	1			T33	4		T34	3		T1	32
all_values[12]	auto[1]	auto[1]	auto[1]	29570	1			T33	2		T34	1		T1	19
all_values[13]	auto[0]	auto[0]	auto[0]	2342478	1			T24	122		T25	156		T26	398
all_values[13]	auto[0]	auto[0]	auto[1]	1949072	1			T30	81		T33	33		T34	24
all_values[13]	auto[0]	auto[1]	auto[0]	219819	1			T30	21		T33	12		T34	9
all_values[13]	auto[0]	auto[1]	auto[1]	1906224	1			T30	115		T33	8		T34	26
all_values[13]	auto[1]	auto[0]	auto[1]	29460	1			T33	3		T34	1		T1	30
all_values[13]	auto[1]	auto[1]	auto[1]	29253	1			T33	1		T34	3		T1	28
all_values[14]	auto[0]	auto[0]	auto[0]	2341052	1			T24	122		T25	156		T26	398
all_values[14]	auto[0]	auto[0]	auto[1]	1922470	1			T30	55		T33	25		T34	21
all_values[14]	auto[0]	auto[1]	auto[0]	220240	1			T30	61		T33	12		T34	22
all_values[14]	auto[0]	auto[1]	auto[1]	1933890	1			T30	97		T33	6		T34	17
all_values[14]	auto[1]	auto[0]	auto[1]	29145	1			T33	4		T34	1		T1	20
all_values[14]	auto[1]	auto[1]	auto[1]	29509	1			T34	3		T1	24		T17	36
all_values[15]	auto[0]	auto[0]	auto[0]	2341277	1			T24	122		T25	156		T26	398
all_values[15]	auto[0]	auto[0]	auto[1]	1940377	1			T30	92		T33	19		T34	39
all_values[15]	auto[0]	auto[1]	auto[0]	218172	1			T30	13		T33	19		T34	2
all_values[15]	auto[0]	auto[1]	auto[1]	1917960	1			T30	100		T33	11		T34	13
all_values[15]	auto[1]	auto[0]	auto[1]	29248	1			T33	2		T34	4		T1	32
all_values[15]	auto[1]	auto[1]	auto[1]	29272	1			T33	1		T34	1		T1	25
all_values[16]	auto[0]	auto[0]	auto[0]	2343404	1			T24	122		T25	156		T26	398
all_values[16]	auto[0]	auto[0]	auto[1]	1931676	1			T30	101		T33	7		T34	34
all_values[16]	auto[0]	auto[1]	auto[0]	217628	1			T30	22		T33	17		T34	5
all_values[16]	auto[0]	auto[1]	auto[1]	1924923	1			T30	76		T33	29		T34	11
all_values[16]	auto[1]	auto[0]	auto[1]	29606	1			T33	1		T34	3		T1	34
all_values[16]	auto[1]	auto[1]	auto[1]	29069	1			T33	4		T34	2		T1	26
all_values[17]	auto[0]	auto[0]	auto[0]	2347443	1			T24	122		T25	156		T26	398
all_values[17]	auto[0]	auto[0]	auto[1]	1947364	1			T30	106		T33	37		T34	29
all_values[17]	auto[0]	auto[1]	auto[0]	213368	1			T30	46		T33	10		T34	7
all_values[17]	auto[0]	auto[1]	auto[1]	1909429	1			T30	38		T34	29		T62	107
all_values[17]	auto[1]	auto[0]	auto[1]	29800	1			T33	4		T34	5		T1	21
all_values[17]	auto[1]	auto[1]	auto[1]	28902	1			T1	25		T13	3		T17	33
all_values[18]	auto[0]	auto[0]	auto[0]	2346864	1			T24	122		T25	156		T26	398
all_values[18]	auto[0]	auto[0]	auto[1]	1930191	1			T30	128		T33	10		T34	29
all_values[18]	auto[0]	auto[1]	auto[0]	216719	1			T30	9		T33	25		T62	20
all_values[18]	auto[0]	auto[1]	auto[1]	1923734	1			T30	88		T33	16		T34	23
all_values[18]	auto[1]	auto[0]	auto[1]	29705	1			T33	1		T34	5		T1	33
all_values[18]	auto[1]	auto[1]	auto[1]	29093	1			T33	4		T1	22		T13	2
all_values[19]	auto[0]	auto[0]	auto[0]	2343665	1			T24	122		T25	156		T26	398
all_values[19]	auto[0]	auto[0]	auto[1]	1928053	1			T30	91		T33	19		T34	12
all_values[19]	auto[0]	auto[1]	auto[0]	217304	1			T30	43		T33	7		T34	8
all_values[19]	auto[0]	auto[1]	auto[1]	1928429	1			T30	63		T33	34		T34	21
all_values[19]	auto[1]	auto[0]	auto[1]	29540	1			T33	4		T34	4		T1	25
all_values[19]	auto[1]	auto[1]	auto[1]	29315	1			T33	4		T1	26		T17	34
all_values[20]	auto[0]	auto[0]	auto[0]	2345854	1			T24	122		T25	156		T26	398
all_values[20]	auto[0]	auto[0]	auto[1]	1937693	1			T30	90		T33	30		T34	13
all_values[20]	auto[0]	auto[1]	auto[0]	217215	1			T30	36		T33	27		T34	13
all_values[20]	auto[0]	auto[1]	auto[1]	1916536	1			T30	50		T33	16		T34	30
all_values[20]	auto[1]	auto[0]	auto[1]	30000	1			T33	3		T34	2		T1	21
all_values[20]	auto[1]	auto[1]	auto[1]	29008	1			T34	2		T1	23		T17	41
all_values[21]	auto[0]	auto[0]	auto[0]	2347181	1			T24	122		T25	156		T26	398
all_values[21]	auto[0]	auto[0]	auto[1]	1934420	1			T30	76		T33	43		T34	5
all_values[21]	auto[0]	auto[1]	auto[0]	218578	1			T30	10		T33	5		T34	26
all_values[21]	auto[0]	auto[1]	auto[1]	1917129	1			T30	125		T33	3		T34	15
all_values[21]	auto[1]	auto[0]	auto[1]	30021	1			T33	5		T34	1		T1	33
all_values[21]	auto[1]	auto[1]	auto[1]	28977	1			T34	1		T1	23		T13	4
all_values[22]	auto[0]	auto[0]	auto[0]	2337802	1			T24	122		T25	156		T26	398
all_values[22]	auto[0]	auto[0]	auto[1]	1925482	1			T30	72		T33	20		T34	7
all_values[22]	auto[0]	auto[1]	auto[0]	221363	1			T30	57		T33	13		T34	22
all_values[22]	auto[0]	auto[1]	auto[1]	1932960	1			T30	90		T34	31		T62	73
all_values[22]	auto[1]	auto[0]	auto[1]	29323	1			T33	3		T34	2		T1	29
all_values[22]	auto[1]	auto[1]	auto[1]	29376	1			T34	1		T1	27		T13	4
all_values[23]	auto[0]	auto[0]	auto[0]	2341227	1			T24	122		T25	156		T26	398
all_values[23]	auto[0]	auto[0]	auto[1]	1926411	1			T30	68		T33	18		T34	16
all_values[23]	auto[0]	auto[1]	auto[0]	222472	1			T30	18		T33	16		T34	16
all_values[23]	auto[0]	auto[1]	auto[1]	1927301	1			T30	119		T33	3		T34	23
all_values[23]	auto[1]	auto[0]	auto[1]	29370	1			T33	4		T34	2		T1	25
all_values[23]	auto[1]	auto[1]	auto[1]	29525	1			T33	3		T34	4		T1	27
all_values[24]	auto[0]	auto[0]	auto[0]	2341404	1			T24	122		T25	156		T26	398
all_values[24]	auto[0]	auto[0]	auto[1]	1932967	1			T30	101		T33	34		T34	27
all_values[24]	auto[0]	auto[1]	auto[0]	216416	1			T30	8		T33	10		T34	19
all_values[24]	auto[0]	auto[1]	auto[1]	1926425	1			T30	95		T33	14		T34	14
all_values[24]	auto[1]	auto[0]	auto[1]	29775	1			T33	3		T34	2		T1	33
all_values[24]	auto[1]	auto[1]	auto[1]	29319	1			T33	2		T34	1		T1	20
all_values[25]	auto[0]	auto[0]	auto[0]	2345629	1			T24	122		T25	156		T26	398
all_values[25]	auto[0]	auto[0]	auto[1]	1933434	1			T30	115		T33	29		T34	19
all_values[25]	auto[0]	auto[1]	auto[0]	218067	1			T30	22		T33	5		T34	25
all_values[25]	auto[0]	auto[1]	auto[1]	1920280	1			T30	92		T33	25		T34	18
all_values[25]	auto[1]	auto[0]	auto[1]	29661	1			T33	5		T34	1		T1	34
all_values[25]	auto[1]	auto[1]	auto[1]	29235	1			T34	1		T1	30		T13	2
all_values[26]	auto[0]	auto[0]	auto[0]	2343415	1			T24	122		T25	156		T26	398
all_values[26]	auto[0]	auto[0]	auto[1]	1944318	1			T30	94		T33	27		T34	30
all_values[26]	auto[0]	auto[1]	auto[0]	215420	1			T30	29		T33	16		T34	8
all_values[26]	auto[0]	auto[1]	auto[1]	1914451	1			T30	75		T33	13		T34	24
all_values[26]	auto[1]	auto[0]	auto[1]	29461	1			T33	2		T34	2		T1	26
all_values[26]	auto[1]	auto[1]	auto[1]	29241	1			T33	2		T34	1		T1	24
all_values[27]	auto[0]	auto[0]	auto[0]	2342705	1			T24	122		T25	156		T26	398
all_values[27]	auto[0]	auto[0]	auto[1]	1937005	1			T30	110		T33	17		T34	22
all_values[27]	auto[0]	auto[1]	auto[0]	217741	1			T30	7		T33	28		T34	4
all_values[27]	auto[0]	auto[1]	auto[1]	1920078	1			T30	102		T33	8		T34	24
all_values[27]	auto[1]	auto[0]	auto[1]	29494	1			T33	3		T1	28		T13	5
all_values[27]	auto[1]	auto[1]	auto[1]	29283	1			T33	3		T34	2		T1	32
all_values[28]	auto[0]	auto[0]	auto[0]	2343267	1			T24	122		T25	156		T26	398
all_values[28]	auto[0]	auto[0]	auto[1]	1936440	1			T30	67		T33	22		T34	21
all_values[28]	auto[0]	auto[1]	auto[0]	218736	1			T30	28		T33	10		T34	25
all_values[28]	auto[0]	auto[1]	auto[1]	1918872	1			T30	100		T33	20		T34	11
all_values[28]	auto[1]	auto[0]	auto[1]	29758	1			T33	3		T34	2		T1	22
all_values[28]	auto[1]	auto[1]	auto[1]	29233	1			T33	2		T34	2		T1	20
all_values[29]	auto[0]	auto[0]	auto[0]	2344424	1			T24	122		T25	156		T26	398
all_values[29]	auto[0]	auto[0]	auto[1]	1944115	1			T30	134		T33	37		T34	21
all_values[29]	auto[0]	auto[1]	auto[0]	216189	1			T30	30		T33	9		T34	14
all_values[29]	auto[0]	auto[1]	auto[1]	1912836	1			T30	52		T33	12		T34	21
all_values[29]	auto[1]	auto[0]	auto[1]	29672	1			T33	4		T34	1		T1	40
all_values[29]	auto[1]	auto[1]	auto[1]	29070	1			T33	1		T34	1		T1	18
all_values[30]	auto[0]	auto[0]	auto[0]	2343806	1			T24	122		T25	156		T26	398
all_values[30]	auto[0]	auto[0]	auto[1]	1929957	1			T30	68		T33	45		T34	30
all_values[30]	auto[0]	auto[1]	auto[0]	219503	1			T30	16		T33	11		T34	13
all_values[30]	auto[0]	auto[1]	auto[1]	1924141	1			T30	120		T33	10		T34	24
all_values[30]	auto[1]	auto[0]	auto[1]	29890	1			T33	4		T34	1		T1	30
all_values[30]	auto[1]	auto[1]	auto[1]	29009	1			T33	2		T1	23		T13	4
all_values[31]	auto[0]	auto[0]	auto[0]	2342868	1			T24	122		T25	156		T26	398
all_values[31]	auto[0]	auto[0]	auto[1]	1933941	1			T30	83		T33	41		T34	16
all_values[31]	auto[0]	auto[1]	auto[0]	217351	1			T30	17		T33	4		T34	14
all_values[31]	auto[0]	auto[1]	auto[1]	1923599	1			T30	121		T33	13		T34	21
all_values[31]	auto[1]	auto[0]	auto[1]	29514	1			T33	3		T34	3		T1	21
all_values[31]	auto[1]	auto[1]	auto[1]	29033	1			T33	1		T34	2		T1	30

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal