Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	6445390	1			T24	184		T25	302		T26	742
bins_for_gpio_bits[1]	6445390	1			T24	184		T25	302		T26	742
bins_for_gpio_bits[2]	6445390	1			T24	184		T25	302		T26	742
bins_for_gpio_bits[3]	6445390	1			T24	184		T25	302		T26	742
bins_for_gpio_bits[4]	6445390	1			T24	184		T25	302		T26	742
bins_for_gpio_bits[5]	6445390	1			T24	184		T25	302		T26	742
bins_for_gpio_bits[6]	6445390	1			T24	184		T25	302		T26	742
bins_for_gpio_bits[7]	6445390	1			T24	184		T25	302		T26	742
bins_for_gpio_bits[8]	6445390	1			T24	184		T25	302		T26	742
bins_for_gpio_bits[9]	6445390	1			T24	184		T25	302		T26	742
bins_for_gpio_bits[10]	6445390	1			T24	184		T25	302		T26	742
bins_for_gpio_bits[11]	6445390	1			T24	184		T25	302		T26	742
bins_for_gpio_bits[12]	6445390	1			T24	184		T25	302		T26	742
bins_for_gpio_bits[13]	6445390	1			T24	184		T25	302		T26	742
bins_for_gpio_bits[14]	6445390	1			T24	184		T25	302		T26	742
bins_for_gpio_bits[15]	6445390	1			T24	184		T25	302		T26	742
bins_for_gpio_bits[16]	6445390	1			T24	184		T25	302		T26	742
bins_for_gpio_bits[17]	6445390	1			T24	184		T25	302		T26	742
bins_for_gpio_bits[18]	6445390	1			T24	184		T25	302		T26	742
bins_for_gpio_bits[19]	6445390	1			T24	184		T25	302		T26	742
bins_for_gpio_bits[20]	6445390	1			T24	184		T25	302		T26	742
bins_for_gpio_bits[21]	6445390	1			T24	184		T25	302		T26	742
bins_for_gpio_bits[22]	6445390	1			T24	184		T25	302		T26	742
bins_for_gpio_bits[23]	6445390	1			T24	184		T25	302		T26	742
bins_for_gpio_bits[24]	6445390	1			T24	184		T25	302		T26	742
bins_for_gpio_bits[25]	6445390	1			T24	184		T25	302		T26	742
bins_for_gpio_bits[26]	6445390	1			T24	184		T25	302		T26	742
bins_for_gpio_bits[27]	6445390	1			T24	184		T25	302		T26	742
bins_for_gpio_bits[28]	6445390	1			T24	184		T25	302		T26	742
bins_for_gpio_bits[29]	6445390	1			T24	184		T25	302		T26	742
bins_for_gpio_bits[30]	6445390	1			T24	184		T25	302		T26	742
bins_for_gpio_bits[31]	6445390	1			T24	184		T25	302		T26	742

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

106648767

1

T24

4008

T25

7637

T26

6349

auto[1]

99603713

1

T24

1880

T25

2027

T26

17395

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

171365436

1

T24

3994

T25

7211

T26

12705

auto[1]

34887044

1

T24

1894

T25

2453

T26

11039

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

161256961

1

T24

4000

T25

4928

T26

12586

auto[1]

44995519

1

T24

1888

T25

4736

T26

11158

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	2302647	1			T24	57		T25	103		T26	33
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	2184324	1			T24	28		T25	11		T26	212
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	548583	1			T24	32		T25	63		T26	134
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	487420	1			T24	30		T25	79		T27	148
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	379618	1			T25	18		T26	188		T27	19
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	542798	1			T24	37		T25	28		T26	175
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	2296414	1			T24	73		T25	89		T26	26
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	2192723	1			T24	27		T25	22		T26	203
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	547933	1			T24	28		T25	42		T26	177
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	483666	1			T24	32		T25	97		T27	173
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	378968	1			T25	10		T26	168		T27	21
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	545686	1			T24	24		T25	42		T26	168
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	2291765	1			T24	62		T25	75		T26	23
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	2196357	1			T24	37		T25	11		T26	172
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	550332	1			T24	26		T25	35		T26	180
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	484117	1			T24	37		T25	119		T27	178
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	379361	1			T25	19		T26	174		T27	28
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	543458	1			T24	22		T25	43		T26	193
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	2297024	1			T24	57		T25	90		T26	25
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	2191595	1			T24	33		T25	6		T26	242
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	550376	1			T24	38		T25	52		T26	187
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	485748	1			T24	26		T25	106		T27	165
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	380177	1			T25	17		T26	146		T27	32
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	540470	1			T24	30		T25	31		T26	142
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	2294643	1			T24	54		T25	141		T26	26
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	2196256	1			T24	31		T25	13		T26	179
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	546080	1			T24	20		T25	34		T26	194
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	485440	1			T24	50		T25	69		T27	150
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	380222	1			T25	5		T26	172		T27	21
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	542749	1			T24	29		T25	40		T26	171
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	2294656	1			T24	76		T25	97		T26	26
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	2194808	1			T24	33		T25	18		T26	183
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	545443	1			T24	27		T25	40		T26	198
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	485955	1			T24	26		T25	111		T27	136
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	377966	1			T25	6		T26	177		T27	12
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	546562	1			T24	22		T25	30		T26	158
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	2292755	1			T24	72		T25	102		T26	25
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	2194225	1			T24	29		T25	8		T26	218
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	546080	1			T24	31		T25	20		T26	180
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	486327	1			T24	26		T25	96		T27	172
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	381203	1			T25	25		T26	175		T27	15
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	544800	1			T24	26		T25	51		T26	144
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	2301188	1			T24	62		T25	129		T26	21
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	2189439	1			T24	28		T25	17		T26	208
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	552902	1			T24	38		T25	67		T26	178
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	483510	1			T24	30		T25	60		T27	196
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	376840	1			T25	3		T26	169		T27	28
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	541511	1			T24	26		T25	26		T26	166
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	2304488	1			T24	55		T25	119		T26	20
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	2193320	1			T24	29		T25	18		T26	255
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	548339	1			T24	40		T25	34		T26	156
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	480155	1			T24	28		T25	95		T27	195
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	377379	1			T25	21		T26	175		T27	21
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	541709	1			T24	32		T25	15		T26	136
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	2293711	1			T24	48		T25	76		T26	27
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	2194582	1			T24	29		T25	5		T26	199
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	548467	1			T24	28		T25	58		T26	156
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	485876	1			T24	30		T25	90		T27	213
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	378806	1			T25	23		T26	172		T27	35
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	543948	1			T24	49		T25	50		T26	188
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	2295230	1			T24	52		T25	79		T26	24
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	2193024	1			T24	30		T25	4		T26	227
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	548285	1			T24	34		T25	15		T26	140
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	487540	1			T24	34		T25	152		T27	185
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	378237	1			T25	8		T26	190		T27	12
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	543074	1			T24	34		T25	44		T26	161
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	2310170	1			T24	84		T25	95		T26	28
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	2181790	1			T24	27		T25	14		T26	159
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	549338	1			T24	22		T25	59		T26	183
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	480694	1			T24	37		T25	73		T27	212
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	377494	1			T25	13		T26	142		T27	30
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	545904	1			T24	14		T25	48		T26	230
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	2303843	1			T24	60		T25	93		T26	23
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	2183713	1			T24	35		T25	17		T26	191
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	548600	1			T24	30		T25	54		T26	148
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	484203	1			T24	20		T25	91		T27	225
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	379699	1			T25	10		T26	196		T27	30
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	545332	1			T24	39		T25	37		T26	184
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	2292911	1			T24	67		T25	125		T26	30
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	2197251	1			T24	26		T25	16		T26	169
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	549383	1			T24	31		T25	50		T26	148
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	485707	1			T24	22		T25	76		T27	152
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	379354	1			T25	6		T26	187		T27	29
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	540784	1			T24	38		T25	29		T26	208
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	2297667	1			T24	72		T25	83		T26	27
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	2191937	1			T24	31		T25	10		T26	198
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	548687	1			T24	34		T25	22		T26	186
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	485593	1			T24	16		T25	114		T27	237
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	378158	1			T25	21		T26	172		T27	26
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	543348	1			T24	31		T25	52		T26	159
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	2292626	1			T24	50		T25	93		T26	27
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	2199580	1			T24	29		T25	18		T26	190
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	548199	1			T24	29		T25	25		T26	154
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	481393	1			T24	28		T25	89		T27	157
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	378463	1			T25	8		T26	193		T27	21
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	545129	1			T24	48		T25	69		T26	178
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	2295290	1			T24	72		T25	78		T26	26
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	2194441	1			T24	23		T25	7		T26	193
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	547487	1			T24	50		T25	50		T26	156
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	486383	1			T24	13		T25	92		T27	205
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	380932	1			T25	21		T26	198		T27	23
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	540857	1			T24	26		T25	54		T26	169
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	2297839	1			T24	79		T25	110		T26	30
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	2192646	1			T24	33		T25	23		T26	187
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	547037	1			T24	32		T25	36		T26	198
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	487124	1			T24	24		T25	113		T27	212
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	378960	1			T25	7		T26	177		T27	30
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	541784	1			T24	16		T25	13		T26	150
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	2305172	1			T24	64		T25	76		T26	31
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	2190845	1			T24	38		T25	14		T26	171
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	546473	1			T24	34		T25	35		T26	176
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	484095	1			T24	18		T25	133		T27	194
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	377460	1			T25	12		T26	184		T27	14
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	541345	1			T24	30		T25	32		T26	180
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	2295690	1			T24	62		T25	91		T26	30
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	2193623	1			T24	27		T25	9		T26	213
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	545984	1			T24	32		T25	60		T26	167
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	487099	1			T24	34		T25	92		T27	148
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	381198	1			T25	11		T26	186		T27	18
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	541796	1			T24	29		T25	39		T26	146
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	2312644	1			T24	91		T25	100		T26	26
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	2186365	1			T24	21		T25	14		T26	174
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	545926	1			T24	40		T25	20		T26	186
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	486007	1			T24	20		T25	121		T27	161
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	378589	1			T25	15		T26	174		T27	12
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	535859	1			T24	12		T25	32		T26	182
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	2308950	1			T24	63		T25	112		T26	28
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	2186512	1			T24	26		T25	15		T26	143
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	546837	1			T24	31		T25	44		T26	168
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	484885	1			T24	30		T25	87		T27	109
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	378791	1			T25	9		T26	223		T27	9
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	539415	1			T24	34		T25	35		T26	180
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	2308810	1			T24	60		T25	79		T26	31
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	2182942	1			T24	36		T25	11		T26	210
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	548957	1			T24	32		T25	22		T26	210
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	484165	1			T24	24		T25	144		T27	275
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	379645	1			T25	17		T26	152		T27	27
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	540871	1			T24	32		T25	29		T26	139
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	2300652	1			T24	57		T25	124		T26	22
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	2192508	1			T24	30		T25	11		T26	223
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	548534	1			T24	14		T25	11		T26	169
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	485000	1			T24	40		T25	103		T27	200
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	379244	1			T25	10		T26	180		T27	19
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	539452	1			T24	43		T25	43		T26	148
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	2299795	1			T24	69		T25	92		T26	27
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	2190504	1			T24	30		T25	13		T26	208
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	544794	1			T24	22		T25	42		T26	163
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	486511	1			T24	40		T25	87		T27	216
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	381857	1			T25	15		T26	170		T27	23
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	541929	1			T24	23		T25	53		T26	174
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	2294289	1			T24	63		T25	87		T26	21
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	2198104	1			T24	32		T25	15		T26	206
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	548842	1			T24	18		T25	44		T26	152
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	483997	1			T24	53		T25	101		T27	149
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	378465	1			T25	16		T26	147		T27	14
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	541693	1			T24	18		T25	39		T26	216
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	2300640	1			T24	88		T25	154		T26	27
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	2190402	1			T24	21		T25	14		T26	185
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	547044	1			T24	16		T25	20		T26	166
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	488247	1			T24	22		T25	66		T27	152
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	379985	1			T25	6		T26	174		T27	12
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	539072	1			T24	37		T25	42		T26	190
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	2306716	1			T24	73		T25	108		T26	21
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	2188785	1			T24	24		T25	14		T26	174
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	548488	1			T24	16		T25	41		T26	192
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	482716	1			T24	31		T25	94		T27	158
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	378054	1			T25	10		T26	167		T27	8
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	540631	1			T24	40		T25	35		T26	188
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	2303470	1			T24	65		T25	118		T26	23
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	2188085	1			T24	28		T25	11		T26	160
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	549118	1			T24	23		T25	4		T26	168
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	486382	1			T24	38		T25	138		T27	220
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	377888	1			T25	12		T26	187		T27	26
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	540447	1			T24	30		T25	19		T26	204
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	2302161	1			T24	71		T25	89		T26	25
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	2186864	1			T24	28		T25	19		T26	190
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	549684	1			T24	46		T25	40		T26	179
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	484691	1			T24	24		T25	95		T27	186
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	380170	1			T25	13		T26	198		T27	26
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	541820	1			T24	15		T25	46		T26	150
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	2303698	1			T24	57		T25	90		T26	29
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	2188668	1			T24	30		T25	15		T26	190
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	548827	1			T24	34		T25	39		T26	171
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	482979	1			T24	32		T25	109		T27	149
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	378245	1			T25	11		T26	186		T27	19
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	542973	1			T24	31		T25	38		T26	166
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	2293845	1			T24	81		T25	138		T26	21
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	2200498	1			T24	26		T25	19		T26	205
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	547787	1			T24	21		T25	83		T26	200
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	484897	1			T24	28		T25	49		T27	231
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	377371	1			T25	5		T26	140		T27	17
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	540992	1			T24	28		T25	8		T26	176

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal