Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	6445390	1			T24	184		T25	302		T26	742
bins_for_gpio_bits[1]	6445390	1			T24	184		T25	302		T26	742
bins_for_gpio_bits[2]	6445390	1			T24	184		T25	302		T26	742
bins_for_gpio_bits[3]	6445390	1			T24	184		T25	302		T26	742
bins_for_gpio_bits[4]	6445390	1			T24	184		T25	302		T26	742
bins_for_gpio_bits[5]	6445390	1			T24	184		T25	302		T26	742
bins_for_gpio_bits[6]	6445390	1			T24	184		T25	302		T26	742
bins_for_gpio_bits[7]	6445390	1			T24	184		T25	302		T26	742
bins_for_gpio_bits[8]	6445390	1			T24	184		T25	302		T26	742
bins_for_gpio_bits[9]	6445390	1			T24	184		T25	302		T26	742
bins_for_gpio_bits[10]	6445390	1			T24	184		T25	302		T26	742
bins_for_gpio_bits[11]	6445390	1			T24	184		T25	302		T26	742
bins_for_gpio_bits[12]	6445390	1			T24	184		T25	302		T26	742
bins_for_gpio_bits[13]	6445390	1			T24	184		T25	302		T26	742
bins_for_gpio_bits[14]	6445390	1			T24	184		T25	302		T26	742
bins_for_gpio_bits[15]	6445390	1			T24	184		T25	302		T26	742
bins_for_gpio_bits[16]	6445390	1			T24	184		T25	302		T26	742
bins_for_gpio_bits[17]	6445390	1			T24	184		T25	302		T26	742
bins_for_gpio_bits[18]	6445390	1			T24	184		T25	302		T26	742
bins_for_gpio_bits[19]	6445390	1			T24	184		T25	302		T26	742
bins_for_gpio_bits[20]	6445390	1			T24	184		T25	302		T26	742
bins_for_gpio_bits[21]	6445390	1			T24	184		T25	302		T26	742
bins_for_gpio_bits[22]	6445390	1			T24	184		T25	302		T26	742
bins_for_gpio_bits[23]	6445390	1			T24	184		T25	302		T26	742
bins_for_gpio_bits[24]	6445390	1			T24	184		T25	302		T26	742
bins_for_gpio_bits[25]	6445390	1			T24	184		T25	302		T26	742
bins_for_gpio_bits[26]	6445390	1			T24	184		T25	302		T26	742
bins_for_gpio_bits[27]	6445390	1			T24	184		T25	302		T26	742
bins_for_gpio_bits[28]	6445390	1			T24	184		T25	302		T26	742
bins_for_gpio_bits[29]	6445390	1			T24	184		T25	302		T26	742
bins_for_gpio_bits[30]	6445390	1			T24	184		T25	302		T26	742
bins_for_gpio_bits[31]	6445390	1			T24	184		T25	302		T26	742

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

106648767

1

T24

4008

T25

7637

T26

6349

auto[1]

99603713

1

T24

1880

T25

2027

T26

17395

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

106641870

1

T24

3997

T25

7634

T26

6357

auto[1]

99610610

1

T24

1891

T25

2030

T26

17387

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	3239238	1			T24	110		T25	240		T26	127
bins_for_gpio_bits[0]	auto[0]	auto[1]	99243	1			T24	8		T25	5		T26	40
bins_for_gpio_bits[0]	auto[1]	auto[0]	99412	1			T24	9		T25	5		T26	40
bins_for_gpio_bits[0]	auto[1]	auto[1]	3007497	1			T24	57		T25	52		T26	535
bins_for_gpio_bits[1]	auto[0]	auto[0]	3228535	1			T24	124		T25	217		T26	159
bins_for_gpio_bits[1]	auto[0]	auto[1]	99254	1			T24	9		T25	11		T26	45
bins_for_gpio_bits[1]	auto[1]	auto[0]	99478	1			T24	9		T25	11		T26	44
bins_for_gpio_bits[1]	auto[1]	auto[1]	3018123	1			T24	42		T25	63		T26	494
bins_for_gpio_bits[2]	auto[0]	auto[0]	3226907	1			T24	117		T25	220		T26	166
bins_for_gpio_bits[2]	auto[0]	auto[1]	99049	1			T24	8		T25	9		T26	37
bins_for_gpio_bits[2]	auto[1]	auto[0]	99307	1			T24	8		T25	9		T26	37
bins_for_gpio_bits[2]	auto[1]	auto[1]	3020127	1			T24	51		T25	64		T26	502
bins_for_gpio_bits[3]	auto[0]	auto[0]	3234041	1			T24	112		T25	243		T26	169
bins_for_gpio_bits[3]	auto[0]	auto[1]	98861	1			T24	9		T25	5		T26	44
bins_for_gpio_bits[3]	auto[1]	auto[0]	99107	1			T24	9		T25	5		T26	43
bins_for_gpio_bits[3]	auto[1]	auto[1]	3013381	1			T24	54		T25	49		T26	486
bins_for_gpio_bits[4]	auto[0]	auto[0]	3226936	1			T24	116		T25	238		T26	175
bins_for_gpio_bits[4]	auto[0]	auto[1]	99009	1			T24	7		T25	6		T26	45
bins_for_gpio_bits[4]	auto[1]	auto[0]	99227	1			T24	8		T25	6		T26	45
bins_for_gpio_bits[4]	auto[1]	auto[1]	3020218	1			T24	53		T25	52		T26	477
bins_for_gpio_bits[5]	auto[0]	auto[0]	3226776	1			T24	124		T25	242		T26	177
bins_for_gpio_bits[5]	auto[0]	auto[1]	99098	1			T24	5		T25	6		T26	47
bins_for_gpio_bits[5]	auto[1]	auto[0]	99278	1			T24	5		T25	6		T26	47
bins_for_gpio_bits[5]	auto[1]	auto[1]	3020238	1			T24	50		T25	48		T26	471
bins_for_gpio_bits[6]	auto[0]	auto[0]	3226005	1			T24	120		T25	209		T26	159
bins_for_gpio_bits[6]	auto[0]	auto[1]	98942	1			T24	9		T25	9		T26	46
bins_for_gpio_bits[6]	auto[1]	auto[0]	99157	1			T24	9		T25	9		T26	46
bins_for_gpio_bits[6]	auto[1]	auto[1]	3021286	1			T24	46		T25	75		T26	491
bins_for_gpio_bits[7]	auto[0]	auto[0]	3238100	1			T24	122		T25	250		T26	157
bins_for_gpio_bits[7]	auto[0]	auto[1]	99282	1			T24	8		T25	6		T26	42
bins_for_gpio_bits[7]	auto[1]	auto[0]	99500	1			T24	8		T25	6		T26	42
bins_for_gpio_bits[7]	auto[1]	auto[1]	3008508	1			T24	46		T25	40		T26	501
bins_for_gpio_bits[8]	auto[0]	auto[0]	3233850	1			T24	111		T25	243		T26	137
bins_for_gpio_bits[8]	auto[0]	auto[1]	98920	1			T24	12		T25	5		T26	39
bins_for_gpio_bits[8]	auto[1]	auto[0]	99132	1			T24	12		T25	5		T26	39
bins_for_gpio_bits[8]	auto[1]	auto[1]	3013488	1			T24	49		T25	49		T26	527
bins_for_gpio_bits[9]	auto[0]	auto[0]	3229109	1			T24	97		T25	216		T26	148
bins_for_gpio_bits[9]	auto[0]	auto[1]	98727	1			T24	8		T25	8		T26	35
bins_for_gpio_bits[9]	auto[1]	auto[0]	98945	1			T24	9		T25	8		T26	35
bins_for_gpio_bits[9]	auto[1]	auto[1]	3018609	1			T24	70		T25	70		T26	524
bins_for_gpio_bits[10]	auto[0]	auto[0]	3231649	1			T24	112		T25	238		T26	128
bins_for_gpio_bits[10]	auto[0]	auto[1]	99220	1			T24	8		T25	8		T26	36
bins_for_gpio_bits[10]	auto[1]	auto[0]	99406	1			T24	8		T25	8		T26	36
bins_for_gpio_bits[10]	auto[1]	auto[1]	3015115	1			T24	56		T25	48		T26	542
bins_for_gpio_bits[11]	auto[0]	auto[0]	3240739	1			T24	137		T25	215		T26	164
bins_for_gpio_bits[11]	auto[0]	auto[1]	99284	1			T24	6		T25	12		T26	48
bins_for_gpio_bits[11]	auto[1]	auto[0]	99463	1			T24	6		T25	12		T26	47
bins_for_gpio_bits[11]	auto[1]	auto[1]	3005904	1			T24	35		T25	63		T26	483
bins_for_gpio_bits[12]	auto[0]	auto[0]	3237489	1			T24	102		T25	229		T26	131
bins_for_gpio_bits[12]	auto[0]	auto[1]	98942	1			T24	7		T25	9		T26	40
bins_for_gpio_bits[12]	auto[1]	auto[0]	99157	1			T24	8		T25	9		T26	40
bins_for_gpio_bits[12]	auto[1]	auto[1]	3009802	1			T24	67		T25	55		T26	531
bins_for_gpio_bits[13]	auto[0]	auto[0]	3228844	1			T24	111		T25	245		T26	136
bins_for_gpio_bits[13]	auto[0]	auto[1]	98948	1			T24	9		T25	6		T26	42
bins_for_gpio_bits[13]	auto[1]	auto[0]	99157	1			T24	9		T25	6		T26	42
bins_for_gpio_bits[13]	auto[1]	auto[1]	3018441	1			T24	55		T25	45		T26	522
bins_for_gpio_bits[14]	auto[0]	auto[0]	3233031	1			T24	113		T25	211		T26	168
bins_for_gpio_bits[14]	auto[0]	auto[1]	98693	1			T24	8		T25	8		T26	45
bins_for_gpio_bits[14]	auto[1]	auto[0]	98916	1			T24	9		T25	8		T26	45
bins_for_gpio_bits[14]	auto[1]	auto[1]	3014750	1			T24	54		T25	75		T26	484
bins_for_gpio_bits[15]	auto[0]	auto[0]	3223272	1			T24	96		T25	199		T26	137
bins_for_gpio_bits[15]	auto[0]	auto[1]	98736	1			T24	11		T25	8		T26	44
bins_for_gpio_bits[15]	auto[1]	auto[0]	98946	1			T24	11		T25	8		T26	44
bins_for_gpio_bits[15]	auto[1]	auto[1]	3024436	1			T24	66		T25	87		T26	517
bins_for_gpio_bits[16]	auto[0]	auto[0]	3230103	1			T24	128		T25	208		T26	139
bins_for_gpio_bits[16]	auto[0]	auto[1]	98854	1			T24	7		T25	11		T26	43
bins_for_gpio_bits[16]	auto[1]	auto[0]	99057	1			T24	7		T25	12		T26	43
bins_for_gpio_bits[16]	auto[1]	auto[1]	3017376	1			T24	42		T25	71		T26	517
bins_for_gpio_bits[17]	auto[0]	auto[0]	3233033	1			T24	130		T25	256		T26	184
bins_for_gpio_bits[17]	auto[0]	auto[1]	98774	1			T24	5		T25	3		T26	44
bins_for_gpio_bits[17]	auto[1]	auto[0]	98967	1			T24	5		T25	3		T26	44
bins_for_gpio_bits[17]	auto[1]	auto[1]	3014616	1			T24	44		T25	40		T26	470
bins_for_gpio_bits[18]	auto[0]	auto[0]	3236584	1			T24	107		T25	238		T26	164
bins_for_gpio_bits[18]	auto[0]	auto[1]	98896	1			T24	9		T25	6		T26	43
bins_for_gpio_bits[18]	auto[1]	auto[0]	99156	1			T24	9		T25	6		T26	43
bins_for_gpio_bits[18]	auto[1]	auto[1]	3010754	1			T24	59		T25	52		T26	492
bins_for_gpio_bits[19]	auto[0]	auto[0]	3229088	1			T24	115		T25	237		T26	149
bins_for_gpio_bits[19]	auto[0]	auto[1]	99434	1			T24	12		T25	6		T26	49
bins_for_gpio_bits[19]	auto[1]	auto[0]	99685	1			T24	13		T25	6		T26	48
bins_for_gpio_bits[19]	auto[1]	auto[1]	3017183	1			T24	44		T25	53		T26	496
bins_for_gpio_bits[20]	auto[0]	auto[0]	3245527	1			T24	147		T25	234		T26	171
bins_for_gpio_bits[20]	auto[0]	auto[1]	98827	1			T24	4		T25	7		T26	41
bins_for_gpio_bits[20]	auto[1]	auto[0]	99050	1			T24	4		T25	7		T26	41
bins_for_gpio_bits[20]	auto[1]	auto[1]	3001986	1			T24	29		T25	54		T26	489
bins_for_gpio_bits[21]	auto[0]	auto[0]	3241276	1			T24	117		T25	235		T26	155
bins_for_gpio_bits[21]	auto[0]	auto[1]	99141	1			T24	7		T25	8		T26	41
bins_for_gpio_bits[21]	auto[1]	auto[0]	99396	1			T24	7		T25	8		T26	41
bins_for_gpio_bits[21]	auto[1]	auto[1]	3005577	1			T24	53		T25	51		T26	505
bins_for_gpio_bits[22]	auto[0]	auto[0]	3242640	1			T24	111		T25	241		T26	196
bins_for_gpio_bits[22]	auto[0]	auto[1]	99076	1			T24	5		T25	4		T26	45
bins_for_gpio_bits[22]	auto[1]	auto[0]	99292	1			T24	5		T25	4		T26	45
bins_for_gpio_bits[22]	auto[1]	auto[1]	3004382	1			T24	63		T25	53		T26	456
bins_for_gpio_bits[23]	auto[0]	auto[0]	3234874	1			T24	102		T25	230		T26	156
bins_for_gpio_bits[23]	auto[0]	auto[1]	99083	1			T24	8		T25	7		T26	36
bins_for_gpio_bits[23]	auto[1]	auto[0]	99312	1			T24	9		T25	8		T26	35
bins_for_gpio_bits[23]	auto[1]	auto[1]	3012121	1			T24	65		T25	57		T26	515
bins_for_gpio_bits[24]	auto[0]	auto[0]	3231658	1			T24	124		T25	211		T26	145
bins_for_gpio_bits[24]	auto[0]	auto[1]	99269	1			T24	6		T25	10		T26	46
bins_for_gpio_bits[24]	auto[1]	auto[0]	99442	1			T24	7		T25	10		T26	45
bins_for_gpio_bits[24]	auto[1]	auto[1]	3015021	1			T24	47		T25	71		T26	506
bins_for_gpio_bits[25]	auto[0]	auto[0]	3227728	1			T24	128		T25	226		T26	133
bins_for_gpio_bits[25]	auto[0]	auto[1]	99185	1			T24	6		T25	6		T26	40
bins_for_gpio_bits[25]	auto[1]	auto[0]	99400	1			T24	6		T25	6		T26	40
bins_for_gpio_bits[25]	auto[1]	auto[1]	3019077	1			T24	44		T25	64		T26	529
bins_for_gpio_bits[26]	auto[0]	auto[0]	3236621	1			T24	120		T25	234		T26	150
bins_for_gpio_bits[26]	auto[0]	auto[1]	99085	1			T24	5		T25	6		T26	43
bins_for_gpio_bits[26]	auto[1]	auto[0]	99310	1			T24	6		T25	6		T26	43
bins_for_gpio_bits[26]	auto[1]	auto[1]	3010374	1			T24	53		T25	56		T26	506
bins_for_gpio_bits[27]	auto[0]	auto[0]	3238505	1			T24	111		T25	237		T26	168
bins_for_gpio_bits[27]	auto[0]	auto[1]	99180	1			T24	9		T25	6		T26	45
bins_for_gpio_bits[27]	auto[1]	auto[0]	99415	1			T24	9		T25	6		T26	45
bins_for_gpio_bits[27]	auto[1]	auto[1]	3008290	1			T24	55		T25	53		T26	484
bins_for_gpio_bits[28]	auto[0]	auto[0]	3239754	1			T24	119		T25	257		T26	155
bins_for_gpio_bits[28]	auto[0]	auto[1]	99051	1			T24	7		T25	3		T26	36
bins_for_gpio_bits[28]	auto[1]	auto[0]	99216	1			T24	7		T25	3		T26	36
bins_for_gpio_bits[28]	auto[1]	auto[1]	3007369	1			T24	51		T25	39		T26	515
bins_for_gpio_bits[29]	auto[0]	auto[0]	3237003	1			T24	136		T25	217		T26	158
bins_for_gpio_bits[29]	auto[0]	auto[1]	99278	1			T24	4		T25	6		T26	47
bins_for_gpio_bits[29]	auto[1]	auto[0]	99533	1			T24	5		T25	7		T26	46
bins_for_gpio_bits[29]	auto[1]	auto[1]	3009576	1			T24	39		T25	72		T26	491
bins_for_gpio_bits[30]	auto[0]	auto[0]	3236321	1			T24	114		T25	230		T26	158
bins_for_gpio_bits[30]	auto[0]	auto[1]	98984	1			T24	8		T25	8		T26	43
bins_for_gpio_bits[30]	auto[1]	auto[0]	99183	1			T24	9		T25	8		T26	42
bins_for_gpio_bits[30]	auto[1]	auto[1]	3010902	1			T24	53		T25	56		T26	499
bins_for_gpio_bits[31]	auto[0]	auto[0]	3227179	1			T24	124		T25	267		T26	177
bins_for_gpio_bits[31]	auto[0]	auto[1]	99130	1			T24	6		T25	3		T26	44
bins_for_gpio_bits[31]	auto[1]	auto[0]	99350	1			T24	6		T25	3		T26	44
bins_for_gpio_bits[31]	auto[1]	auto[1]	3019731	1			T24	48		T25	29		T26	477