Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4310083 |
1 |
|
|
T24 |
122 |
|
T25 |
156 |
|
T26 |
398 |
| auto[1] |
2166223 |
1 |
|
|
T30 |
114 |
|
T33 |
32 |
|
T34 |
18 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6198777 |
1 |
|
|
T24 |
122 |
|
T25 |
156 |
|
T26 |
398 |
| auto[1] |
277529 |
1 |
|
|
T30 |
5 |
|
T33 |
1 |
|
T62 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4301247 |
1 |
|
|
T24 |
122 |
|
T25 |
156 |
|
T26 |
398 |
| auto[1] |
2175059 |
1 |
|
|
T30 |
105 |
|
T33 |
31 |
|
T34 |
25 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
950691 |
1 |
|
|
T30 |
56 |
|
T33 |
15 |
|
T34 |
17 |
| auto[1] |
auto[0] |
auto[1] |
138790 |
1 |
|
|
T30 |
3 |
|
T62 |
2 |
|
T110 |
70 |
| auto[1] |
auto[1] |
auto[0] |
946839 |
1 |
|
|
T30 |
44 |
|
T33 |
15 |
|
T34 |
8 |
| auto[1] |
auto[1] |
auto[1] |
138739 |
1 |
|
|
T30 |
2 |
|
T33 |
1 |
|
T62 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4288472 |
1 |
|
|
T24 |
122 |
|
T25 |
156 |
|
T26 |
398 |
| auto[1] |
2187834 |
1 |
|
|
T30 |
127 |
|
T33 |
40 |
|
T34 |
41 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6197709 |
1 |
|
|
T24 |
122 |
|
T25 |
156 |
|
T26 |
398 |
| auto[1] |
278597 |
1 |
|
|
T30 |
4 |
|
T33 |
2 |
|
T62 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4301201 |
1 |
|
|
T24 |
122 |
|
T25 |
156 |
|
T26 |
398 |
| auto[1] |
2175105 |
1 |
|
|
T30 |
81 |
|
T33 |
35 |
|
T34 |
39 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
944390 |
1 |
|
|
T30 |
49 |
|
T33 |
11 |
|
T34 |
16 |
| auto[1] |
auto[0] |
auto[1] |
138528 |
1 |
|
|
T30 |
3 |
|
T110 |
110 |
|
T111 |
127 |
| auto[1] |
auto[1] |
auto[0] |
952118 |
1 |
|
|
T30 |
28 |
|
T33 |
22 |
|
T34 |
23 |
| auto[1] |
auto[1] |
auto[1] |
140069 |
1 |
|
|
T30 |
1 |
|
T33 |
2 |
|
T62 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4303020 |
1 |
|
|
T24 |
122 |
|
T25 |
156 |
|
T26 |
398 |
| auto[1] |
2173286 |
1 |
|
|
T30 |
119 |
|
T33 |
25 |
|
T34 |
32 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6197165 |
1 |
|
|
T24 |
122 |
|
T25 |
156 |
|
T26 |
398 |
| auto[1] |
279141 |
1 |
|
|
T30 |
4 |
|
T62 |
6 |
|
T110 |
209 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4292007 |
1 |
|
|
T24 |
122 |
|
T25 |
156 |
|
T26 |
398 |
| auto[1] |
2184299 |
1 |
|
|
T30 |
135 |
|
T33 |
37 |
|
T34 |
49 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
949397 |
1 |
|
|
T30 |
50 |
|
T33 |
29 |
|
T34 |
21 |
| auto[1] |
auto[0] |
auto[1] |
139271 |
1 |
|
|
T30 |
2 |
|
T62 |
5 |
|
T110 |
62 |
| auto[1] |
auto[1] |
auto[0] |
955761 |
1 |
|
|
T30 |
81 |
|
T33 |
8 |
|
T34 |
28 |
| auto[1] |
auto[1] |
auto[1] |
139870 |
1 |
|
|
T30 |
2 |
|
T62 |
1 |
|
T110 |
147 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4301530 |
1 |
|
|
T24 |
122 |
|
T25 |
156 |
|
T26 |
398 |
| auto[1] |
2174776 |
1 |
|
|
T30 |
120 |
|
T33 |
14 |
|
T34 |
40 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6199338 |
1 |
|
|
T24 |
122 |
|
T25 |
156 |
|
T26 |
398 |
| auto[1] |
276968 |
1 |
|
|
T30 |
6 |
|
T62 |
6 |
|
T110 |
171 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4312607 |
1 |
|
|
T24 |
122 |
|
T25 |
156 |
|
T26 |
398 |
| auto[1] |
2163699 |
1 |
|
|
T30 |
117 |
|
T33 |
42 |
|
T34 |
29 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
944411 |
1 |
|
|
T30 |
70 |
|
T33 |
40 |
|
T34 |
17 |
| auto[1] |
auto[0] |
auto[1] |
138545 |
1 |
|
|
T30 |
3 |
|
T62 |
3 |
|
T110 |
70 |
| auto[1] |
auto[1] |
auto[0] |
942320 |
1 |
|
|
T30 |
41 |
|
T33 |
2 |
|
T34 |
12 |
| auto[1] |
auto[1] |
auto[1] |
138423 |
1 |
|
|
T30 |
3 |
|
T62 |
3 |
|
T110 |
101 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4303955 |
1 |
|
|
T24 |
122 |
|
T25 |
156 |
|
T26 |
398 |
| auto[1] |
2172351 |
1 |
|
|
T30 |
123 |
|
T33 |
26 |
|
T34 |
38 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6198932 |
1 |
|
|
T24 |
122 |
|
T25 |
156 |
|
T26 |
398 |
| auto[1] |
277374 |
1 |
|
|
T30 |
3 |
|
T33 |
1 |
|
T62 |
9 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4304099 |
1 |
|
|
T24 |
122 |
|
T25 |
156 |
|
T26 |
398 |
| auto[1] |
2172207 |
1 |
|
|
T30 |
91 |
|
T33 |
49 |
|
T34 |
36 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
950320 |
1 |
|
|
T30 |
37 |
|
T33 |
32 |
|
T34 |
16 |
| auto[1] |
auto[0] |
auto[1] |
139152 |
1 |
|
|
T30 |
1 |
|
T33 |
1 |
|
T62 |
3 |
| auto[1] |
auto[1] |
auto[0] |
944513 |
1 |
|
|
T30 |
51 |
|
T33 |
16 |
|
T34 |
20 |
| auto[1] |
auto[1] |
auto[1] |
138222 |
1 |
|
|
T30 |
2 |
|
T62 |
6 |
|
T110 |
108 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4321010 |
1 |
|
|
T24 |
122 |
|
T25 |
156 |
|
T26 |
398 |
| auto[1] |
2155296 |
1 |
|
|
T30 |
136 |
|
T33 |
21 |
|
T34 |
38 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6196030 |
1 |
|
|
T24 |
122 |
|
T25 |
156 |
|
T26 |
398 |
| auto[1] |
280276 |
1 |
|
|
T30 |
5 |
|
T33 |
1 |
|
T62 |
10 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4292561 |
1 |
|
|
T24 |
122 |
|
T25 |
156 |
|
T26 |
398 |
| auto[1] |
2183745 |
1 |
|
|
T30 |
94 |
|
T33 |
48 |
|
T34 |
27 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
958510 |
1 |
|
|
T30 |
37 |
|
T33 |
36 |
|
T34 |
10 |
| auto[1] |
auto[0] |
auto[1] |
141487 |
1 |
|
|
T30 |
1 |
|
T33 |
1 |
|
T62 |
5 |
| auto[1] |
auto[1] |
auto[0] |
944959 |
1 |
|
|
T30 |
52 |
|
T33 |
11 |
|
T34 |
17 |
| auto[1] |
auto[1] |
auto[1] |
138789 |
1 |
|
|
T30 |
4 |
|
T62 |
5 |
|
T110 |
152 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4292667 |
1 |
|
|
T24 |
122 |
|
T25 |
156 |
|
T26 |
398 |
| auto[1] |
2183639 |
1 |
|
|
T30 |
158 |
|
T33 |
18 |
|
T34 |
42 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6199233 |
1 |
|
|
T24 |
122 |
|
T25 |
156 |
|
T26 |
398 |
| auto[1] |
277073 |
1 |
|
|
T30 |
1 |
|
T34 |
1 |
|
T62 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4305528 |
1 |
|
|
T24 |
122 |
|
T25 |
156 |
|
T26 |
398 |
| auto[1] |
2170778 |
1 |
|
|
T30 |
87 |
|
T33 |
35 |
|
T34 |
45 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
942135 |
1 |
|
|
T30 |
23 |
|
T33 |
27 |
|
T34 |
25 |
| auto[1] |
auto[0] |
auto[1] |
137680 |
1 |
|
|
T62 |
2 |
|
T110 |
116 |
|
T111 |
58 |
| auto[1] |
auto[1] |
auto[0] |
951570 |
1 |
|
|
T30 |
63 |
|
T33 |
8 |
|
T34 |
19 |
| auto[1] |
auto[1] |
auto[1] |
139393 |
1 |
|
|
T30 |
1 |
|
T34 |
1 |
|
T62 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4310902 |
1 |
|
|
T24 |
122 |
|
T25 |
156 |
|
T26 |
398 |
| auto[1] |
2165404 |
1 |
|
|
T30 |
113 |
|
T33 |
31 |
|
T34 |
16 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6199009 |
1 |
|
|
T24 |
122 |
|
T25 |
156 |
|
T26 |
398 |
| auto[1] |
277297 |
1 |
|
|
T30 |
4 |
|
T62 |
2 |
|
T110 |
234 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4306793 |
1 |
|
|
T24 |
122 |
|
T25 |
156 |
|
T26 |
398 |
| auto[1] |
2169513 |
1 |
|
|
T30 |
106 |
|
T33 |
35 |
|
T34 |
44 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
948469 |
1 |
|
|
T30 |
53 |
|
T33 |
27 |
|
T34 |
37 |
| auto[1] |
auto[0] |
auto[1] |
139168 |
1 |
|
|
T30 |
1 |
|
T110 |
119 |
|
T111 |
128 |
| auto[1] |
auto[1] |
auto[0] |
943747 |
1 |
|
|
T30 |
49 |
|
T33 |
8 |
|
T34 |
7 |
| auto[1] |
auto[1] |
auto[1] |
138129 |
1 |
|
|
T30 |
3 |
|
T62 |
2 |
|
T110 |
115 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4304686 |
1 |
|
|
T24 |
122 |
|
T25 |
156 |
|
T26 |
398 |
| auto[1] |
2171620 |
1 |
|
|
T30 |
98 |
|
T33 |
50 |
|
T34 |
18 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6202162 |
1 |
|
|
T24 |
122 |
|
T25 |
156 |
|
T26 |
398 |
| auto[1] |
274144 |
1 |
|
|
T30 |
6 |
|
T33 |
3 |
|
T62 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4322688 |
1 |
|
|
T24 |
122 |
|
T25 |
156 |
|
T26 |
398 |
| auto[1] |
2153618 |
1 |
|
|
T30 |
121 |
|
T33 |
35 |
|
T34 |
50 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
945366 |
1 |
|
|
T30 |
64 |
|
T33 |
9 |
|
T34 |
34 |
| auto[1] |
auto[0] |
auto[1] |
137532 |
1 |
|
|
T30 |
6 |
|
T62 |
5 |
|
T110 |
106 |
| auto[1] |
auto[1] |
auto[0] |
934108 |
1 |
|
|
T30 |
51 |
|
T33 |
23 |
|
T34 |
16 |
| auto[1] |
auto[1] |
auto[1] |
136612 |
1 |
|
|
T33 |
3 |
|
T110 |
62 |
|
T111 |
115 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4324607 |
1 |
|
|
T24 |
122 |
|
T25 |
156 |
|
T26 |
398 |
| auto[1] |
2151699 |
1 |
|
|
T30 |
84 |
|
T33 |
10 |
|
T34 |
36 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6199371 |
1 |
|
|
T24 |
122 |
|
T25 |
156 |
|
T26 |
398 |
| auto[1] |
276935 |
1 |
|
|
T30 |
3 |
|
T33 |
1 |
|
T62 |
6 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4307674 |
1 |
|
|
T24 |
122 |
|
T25 |
156 |
|
T26 |
398 |
| auto[1] |
2168632 |
1 |
|
|
T30 |
118 |
|
T33 |
41 |
|
T34 |
46 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
961728 |
1 |
|
|
T30 |
69 |
|
T33 |
40 |
|
T34 |
20 |
| auto[1] |
auto[0] |
auto[1] |
140856 |
1 |
|
|
T30 |
2 |
|
T33 |
1 |
|
T62 |
3 |
| auto[1] |
auto[1] |
auto[0] |
929969 |
1 |
|
|
T30 |
46 |
|
T34 |
26 |
|
T62 |
81 |
| auto[1] |
auto[1] |
auto[1] |
136079 |
1 |
|
|
T30 |
1 |
|
T62 |
3 |
|
T110 |
57 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4306760 |
1 |
|
|
T24 |
122 |
|
T25 |
156 |
|
T26 |
398 |
| auto[1] |
2169546 |
1 |
|
|
T30 |
97 |
|
T33 |
45 |
|
T34 |
23 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6199309 |
1 |
|
|
T24 |
122 |
|
T25 |
156 |
|
T26 |
398 |
| auto[1] |
276997 |
1 |
|
|
T30 |
1 |
|
T33 |
1 |
|
T34 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4309620 |
1 |
|
|
T24 |
122 |
|
T25 |
156 |
|
T26 |
398 |
| auto[1] |
2166686 |
1 |
|
|
T30 |
108 |
|
T33 |
43 |
|
T34 |
40 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
943459 |
1 |
|
|
T30 |
51 |
|
T33 |
14 |
|
T34 |
30 |
| auto[1] |
auto[0] |
auto[1] |
138412 |
1 |
|
|
T30 |
1 |
|
T62 |
7 |
|
T110 |
120 |
| auto[1] |
auto[1] |
auto[0] |
946230 |
1 |
|
|
T30 |
56 |
|
T33 |
28 |
|
T34 |
9 |
| auto[1] |
auto[1] |
auto[1] |
138585 |
1 |
|
|
T33 |
1 |
|
T34 |
1 |
|
T62 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4301258 |
1 |
|
|
T24 |
122 |
|
T25 |
156 |
|
T26 |
398 |
| auto[1] |
2175048 |
1 |
|
|
T30 |
106 |
|
T33 |
45 |
|
T34 |
29 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6200145 |
1 |
|
|
T24 |
122 |
|
T25 |
156 |
|
T26 |
398 |
| auto[1] |
276161 |
1 |
|
|
T30 |
7 |
|
T33 |
2 |
|
T34 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4312348 |
1 |
|
|
T24 |
122 |
|
T25 |
156 |
|
T26 |
398 |
| auto[1] |
2163958 |
1 |
|
|
T30 |
147 |
|
T33 |
58 |
|
T34 |
31 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
942031 |
1 |
|
|
T30 |
82 |
|
T33 |
21 |
|
T34 |
17 |
| auto[1] |
auto[0] |
auto[1] |
137601 |
1 |
|
|
T30 |
2 |
|
T34 |
1 |
|
T62 |
4 |
| auto[1] |
auto[1] |
auto[0] |
945766 |
1 |
|
|
T30 |
58 |
|
T33 |
35 |
|
T34 |
13 |
| auto[1] |
auto[1] |
auto[1] |
138560 |
1 |
|
|
T30 |
5 |
|
T33 |
2 |
|
T62 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4295255 |
1 |
|
|
T24 |
122 |
|
T25 |
156 |
|
T26 |
398 |
| auto[1] |
2181051 |
1 |
|
|
T30 |
107 |
|
T33 |
36 |
|
T34 |
31 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6198289 |
1 |
|
|
T24 |
122 |
|
T25 |
156 |
|
T26 |
398 |
| auto[1] |
278017 |
1 |
|
|
T30 |
3 |
|
T33 |
2 |
|
T62 |
8 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4308006 |
1 |
|
|
T24 |
122 |
|
T25 |
156 |
|
T26 |
398 |
| auto[1] |
2168300 |
1 |
|
|
T30 |
131 |
|
T33 |
56 |
|
T34 |
35 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
941928 |
1 |
|
|
T30 |
75 |
|
T33 |
41 |
|
T34 |
25 |
| auto[1] |
auto[0] |
auto[1] |
138079 |
1 |
|
|
T30 |
3 |
|
T33 |
1 |
|
T62 |
2 |
| auto[1] |
auto[1] |
auto[0] |
948355 |
1 |
|
|
T30 |
53 |
|
T33 |
13 |
|
T34 |
10 |
| auto[1] |
auto[1] |
auto[1] |
139938 |
1 |
|
|
T33 |
1 |
|
T62 |
6 |
|
T110 |
78 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4313547 |
1 |
|
|
T24 |
122 |
|
T25 |
156 |
|
T26 |
398 |
| auto[1] |
2162759 |
1 |
|
|
T30 |
86 |
|
T33 |
43 |
|
T34 |
45 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6199701 |
1 |
|
|
T24 |
122 |
|
T25 |
156 |
|
T26 |
398 |
| auto[1] |
276605 |
1 |
|
|
T30 |
3 |
|
T33 |
1 |
|
T34 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4313477 |
1 |
|
|
T24 |
122 |
|
T25 |
156 |
|
T26 |
398 |
| auto[1] |
2162829 |
1 |
|
|
T30 |
75 |
|
T33 |
46 |
|
T34 |
42 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
950912 |
1 |
|
|
T30 |
51 |
|
T33 |
18 |
|
T34 |
10 |
| auto[1] |
auto[0] |
auto[1] |
139319 |
1 |
|
|
T30 |
3 |
|
T62 |
2 |
|
T110 |
152 |
| auto[1] |
auto[1] |
auto[0] |
935312 |
1 |
|
|
T30 |
21 |
|
T33 |
27 |
|
T34 |
31 |
| auto[1] |
auto[1] |
auto[1] |
137286 |
1 |
|
|
T33 |
1 |
|
T34 |
1 |
|
T62 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4311622 |
1 |
|
|
T24 |
122 |
|
T25 |
156 |
|
T26 |
398 |
| auto[1] |
2164684 |
1 |
|
|
T30 |
135 |
|
T33 |
8 |
|
T34 |
42 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6202154 |
1 |
|
|
T24 |
122 |
|
T25 |
156 |
|
T26 |
398 |
| auto[1] |
274152 |
1 |
|
|
T30 |
5 |
|
T62 |
5 |
|
T110 |
229 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4326438 |
1 |
|
|
T24 |
122 |
|
T25 |
156 |
|
T26 |
398 |
| auto[1] |
2149868 |
1 |
|
|
T30 |
131 |
|
T33 |
35 |
|
T34 |
41 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
943986 |
1 |
|
|
T30 |
62 |
|
T33 |
33 |
|
T34 |
28 |
| auto[1] |
auto[0] |
auto[1] |
137852 |
1 |
|
|
T30 |
3 |
|
T62 |
5 |
|
T110 |
175 |
| auto[1] |
auto[1] |
auto[0] |
931730 |
1 |
|
|
T30 |
64 |
|
T33 |
2 |
|
T34 |
13 |
| auto[1] |
auto[1] |
auto[1] |
136300 |
1 |
|
|
T30 |
2 |
|
T110 |
54 |
|
T111 |
138 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4292607 |
1 |
|
|
T24 |
122 |
|
T25 |
156 |
|
T26 |
398 |
| auto[1] |
2183699 |
1 |
|
|
T30 |
147 |
|
T33 |
13 |
|
T34 |
54 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6202128 |
1 |
|
|
T24 |
122 |
|
T25 |
156 |
|
T26 |
398 |
| auto[1] |
274178 |
1 |
|
|
T30 |
4 |
|
T33 |
1 |
|
T62 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4320372 |
1 |
|
|
T24 |
122 |
|
T25 |
156 |
|
T26 |
398 |
| auto[1] |
2155934 |
1 |
|
|
T30 |
121 |
|
T33 |
35 |
|
T34 |
27 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
939187 |
1 |
|
|
T30 |
45 |
|
T33 |
29 |
|
T34 |
12 |
| auto[1] |
auto[0] |
auto[1] |
136930 |
1 |
|
|
T33 |
1 |
|
T110 |
106 |
|
T111 |
76 |
| auto[1] |
auto[1] |
auto[0] |
942569 |
1 |
|
|
T30 |
72 |
|
T33 |
5 |
|
T34 |
15 |
| auto[1] |
auto[1] |
auto[1] |
137248 |
1 |
|
|
T30 |
4 |
|
T62 |
1 |
|
T110 |
76 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4297008 |
1 |
|
|
T24 |
122 |
|
T25 |
156 |
|
T26 |
398 |
| auto[1] |
2179298 |
1 |
|
|
T30 |
137 |
|
T33 |
22 |
|
T34 |
43 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6199716 |
1 |
|
|
T24 |
122 |
|
T25 |
156 |
|
T26 |
398 |
| auto[1] |
276590 |
1 |
|
|
T30 |
4 |
|
T33 |
1 |
|
T62 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4308878 |
1 |
|
|
T24 |
122 |
|
T25 |
156 |
|
T26 |
398 |
| auto[1] |
2167428 |
1 |
|
|
T30 |
114 |
|
T33 |
35 |
|
T34 |
21 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
944451 |
1 |
|
|
T30 |
30 |
|
T33 |
29 |
|
T34 |
16 |
| auto[1] |
auto[0] |
auto[1] |
138790 |
1 |
|
|
T62 |
4 |
|
T110 |
77 |
|
T111 |
118 |
| auto[1] |
auto[1] |
auto[0] |
946387 |
1 |
|
|
T30 |
80 |
|
T33 |
5 |
|
T34 |
5 |
| auto[1] |
auto[1] |
auto[1] |
137800 |
1 |
|
|
T30 |
4 |
|
T33 |
1 |
|
T62 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |