Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4321010 |
1 |
|
|
T24 |
122 |
|
T25 |
156 |
|
T26 |
398 |
| auto[1] |
2155296 |
1 |
|
|
T30 |
136 |
|
T33 |
21 |
|
T34 |
38 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5437260 |
1 |
|
|
T24 |
122 |
|
T25 |
156 |
|
T26 |
398 |
| auto[1] |
1039046 |
1 |
|
|
T30 |
73 |
|
T33 |
16 |
|
T34 |
17 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4316792 |
1 |
|
|
T24 |
122 |
|
T25 |
156 |
|
T26 |
398 |
| auto[1] |
2159514 |
1 |
|
|
T30 |
165 |
|
T33 |
38 |
|
T34 |
45 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
568210 |
1 |
|
|
T30 |
46 |
|
T33 |
22 |
|
T34 |
12 |
| auto[1] |
auto[0] |
auto[1] |
527138 |
1 |
|
|
T30 |
25 |
|
T33 |
13 |
|
T34 |
9 |
| auto[1] |
auto[1] |
auto[0] |
552258 |
1 |
|
|
T30 |
46 |
|
T34 |
16 |
|
T62 |
47 |
| auto[1] |
auto[1] |
auto[1] |
511908 |
1 |
|
|
T30 |
48 |
|
T33 |
3 |
|
T34 |
8 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |