Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4324607 |
1 |
|
|
T24 |
122 |
|
T25 |
156 |
|
T26 |
398 |
| auto[1] |
2151699 |
1 |
|
|
T30 |
84 |
|
T33 |
10 |
|
T34 |
36 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5434548 |
1 |
|
|
T24 |
122 |
|
T25 |
156 |
|
T26 |
398 |
| auto[1] |
1041758 |
1 |
|
|
T30 |
71 |
|
T33 |
20 |
|
T34 |
31 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4309565 |
1 |
|
|
T24 |
122 |
|
T25 |
156 |
|
T26 |
398 |
| auto[1] |
2166741 |
1 |
|
|
T30 |
110 |
|
T33 |
42 |
|
T34 |
32 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
566596 |
1 |
|
|
T30 |
23 |
|
T33 |
17 |
|
T62 |
15 |
| auto[1] |
auto[0] |
auto[1] |
524867 |
1 |
|
|
T30 |
54 |
|
T33 |
20 |
|
T34 |
12 |
| auto[1] |
auto[1] |
auto[0] |
558387 |
1 |
|
|
T30 |
16 |
|
T33 |
5 |
|
T34 |
1 |
| auto[1] |
auto[1] |
auto[1] |
516891 |
1 |
|
|
T30 |
17 |
|
T34 |
19 |
|
T62 |
15 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |