Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4306760 |
1 |
|
|
T24 |
122 |
|
T25 |
156 |
|
T26 |
398 |
| auto[1] |
2169546 |
1 |
|
|
T30 |
97 |
|
T33 |
45 |
|
T34 |
23 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5441893 |
1 |
|
|
T24 |
122 |
|
T25 |
156 |
|
T26 |
398 |
| auto[1] |
1034413 |
1 |
|
|
T30 |
120 |
|
T33 |
5 |
|
T34 |
17 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4323582 |
1 |
|
|
T24 |
122 |
|
T25 |
156 |
|
T26 |
398 |
| auto[1] |
2152724 |
1 |
|
|
T30 |
153 |
|
T33 |
24 |
|
T34 |
29 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
557160 |
1 |
|
|
T30 |
28 |
|
T33 |
7 |
|
T34 |
10 |
| auto[1] |
auto[0] |
auto[1] |
517889 |
1 |
|
|
T30 |
65 |
|
T33 |
3 |
|
T34 |
8 |
| auto[1] |
auto[1] |
auto[0] |
561151 |
1 |
|
|
T30 |
5 |
|
T33 |
12 |
|
T34 |
2 |
| auto[1] |
auto[1] |
auto[1] |
516524 |
1 |
|
|
T30 |
55 |
|
T33 |
2 |
|
T34 |
9 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |