Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4309465 |
1 |
|
|
T24 |
122 |
|
T25 |
156 |
|
T26 |
398 |
| auto[1] |
2166841 |
1 |
|
|
T30 |
128 |
|
T33 |
32 |
|
T34 |
38 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6201897 |
1 |
|
|
T24 |
122 |
|
T25 |
156 |
|
T26 |
398 |
| auto[1] |
274409 |
1 |
|
|
T30 |
2 |
|
T34 |
1 |
|
T62 |
7 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4323068 |
1 |
|
|
T24 |
122 |
|
T25 |
156 |
|
T26 |
398 |
| auto[1] |
2153238 |
1 |
|
|
T30 |
120 |
|
T33 |
33 |
|
T34 |
39 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
948754 |
1 |
|
|
T30 |
52 |
|
T33 |
28 |
|
T34 |
20 |
| auto[1] |
auto[0] |
auto[1] |
137927 |
1 |
|
|
T62 |
3 |
|
T110 |
66 |
|
T111 |
58 |
| auto[1] |
auto[1] |
auto[0] |
930075 |
1 |
|
|
T30 |
66 |
|
T33 |
5 |
|
T34 |
18 |
| auto[1] |
auto[1] |
auto[1] |
136482 |
1 |
|
|
T30 |
2 |
|
T34 |
1 |
|
T62 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |