Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	1378901	1			T33	1		T34	1		T35	1
all_pins[1]	1378901	1			T33	1		T34	1		T35	1
all_pins[2]	1378901	1			T33	1		T34	1		T35	1
all_pins[3]	1378901	1			T33	1		T34	1		T35	1
all_pins[4]	1378901	1			T33	1		T34	1		T35	1
all_pins[5]	1378901	1			T33	1		T34	1		T35	1
all_pins[6]	1378901	1			T33	1		T34	1		T35	1
all_pins[7]	1378901	1			T33	1		T34	1		T35	1
all_pins[8]	1378901	1			T33	1		T34	1		T35	1
all_pins[9]	1378901	1			T33	1		T34	1		T35	1
all_pins[10]	1378901	1			T33	1		T34	1		T35	1
all_pins[11]	1378901	1			T33	1		T34	1		T35	1
all_pins[12]	1378901	1			T33	1		T34	1		T35	1
all_pins[13]	1378901	1			T33	1		T34	1		T35	1
all_pins[14]	1378901	1			T33	1		T34	1		T35	1
all_pins[15]	1378901	1			T33	1		T34	1		T35	1
all_pins[16]	1378901	1			T33	1		T34	1		T35	1
all_pins[17]	1378901	1			T33	1		T34	1		T35	1
all_pins[18]	1378901	1			T33	1		T34	1		T35	1
all_pins[19]	1378901	1			T33	1		T34	1		T35	1
all_pins[20]	1378901	1			T33	1		T34	1		T35	1
all_pins[21]	1378901	1			T33	1		T34	1		T35	1
all_pins[22]	1378901	1			T33	1		T34	1		T35	1
all_pins[23]	1378901	1			T33	1		T34	1		T35	1
all_pins[24]	1378901	1			T33	1		T34	1		T35	1
all_pins[25]	1378901	1			T33	1		T34	1		T35	1
all_pins[26]	1378901	1			T33	1		T34	1		T35	1
all_pins[27]	1378901	1			T33	1		T34	1		T35	1
all_pins[28]	1378901	1			T33	1		T34	1		T35	1
all_pins[29]	1378901	1			T33	1		T34	1		T35	1
all_pins[30]	1378901	1			T33	1		T34	1		T35	1
all_pins[31]	1378901	1			T33	1		T34	1		T35	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	27432731	1			T33	32		T34	32		T35	32
values[0x1]	16692101	1			T38	1161		T39	480		T40	8740
transitions[0x0=>0x1]	9998631	1			T38	693		T39	252		T40	5125
transitions[0x1=>0x0]	9998474	1			T38	693		T39	252		T40	5124

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	856095	1			T33	1		T34	1		T35	1
all_pins[0]	values[0x1]	522806	1			T38	32		T39	12		T40	365
all_pins[0]	transitions[0x0=>0x1]	324062	1			T38	28		T39	9		T40	249
all_pins[0]	transitions[0x1=>0x0]	321435	1			T38	2		T39	7		T40	131
all_pins[1]	values[0x0]	858637	1			T33	1		T34	1		T35	1
all_pins[1]	values[0x1]	520264	1			T38	31		T39	16		T40	353
all_pins[1]	transitions[0x0=>0x1]	310249	1			T38	20		T39	12		T40	149
all_pins[1]	transitions[0x1=>0x0]	312791	1			T38	21		T39	8		T40	161
all_pins[2]	values[0x0]	858113	1			T33	1		T34	1		T35	1
all_pins[2]	values[0x1]	520788	1			T38	31		T39	16		T40	180
all_pins[2]	transitions[0x0=>0x1]	310875	1			T38	18		T39	6		T40	79
all_pins[2]	transitions[0x1=>0x0]	310351	1			T38	18		T39	6		T40	252
all_pins[3]	values[0x0]	853955	1			T33	1		T34	1		T35	1
all_pins[3]	values[0x1]	524946	1			T38	38		T39	13		T40	289
all_pins[3]	transitions[0x0=>0x1]	312283	1			T38	21		T39	5		T40	233
all_pins[3]	transitions[0x1=>0x0]	308125	1			T38	14		T39	8		T40	124
all_pins[4]	values[0x0]	855478	1			T33	1		T34	1		T35	1
all_pins[4]	values[0x1]	523423	1			T38	41		T39	16		T40	276
all_pins[4]	transitions[0x0=>0x1]	311875	1			T38	22		T39	12		T40	157
all_pins[4]	transitions[0x1=>0x0]	313398	1			T38	19		T39	9		T40	170
all_pins[5]	values[0x0]	856658	1			T33	1		T34	1		T35	1
all_pins[5]	values[0x1]	522243	1			T38	39		T39	11		T40	250
all_pins[5]	transitions[0x0=>0x1]	312298	1			T38	21		T39	4		T40	150
all_pins[5]	transitions[0x1=>0x0]	313478	1			T38	23		T39	9		T40	176
all_pins[6]	values[0x0]	856705	1			T33	1		T34	1		T35	1
all_pins[6]	values[0x1]	522196	1			T38	35		T39	16		T40	188
all_pins[6]	transitions[0x0=>0x1]	312610	1			T38	14		T39	13		T40	120
all_pins[6]	transitions[0x1=>0x0]	312657	1			T38	18		T39	8		T40	182
all_pins[7]	values[0x0]	858682	1			T33	1		T34	1		T35	1
all_pins[7]	values[0x1]	520219	1			T38	29		T39	16		T40	295
all_pins[7]	transitions[0x0=>0x1]	311420	1			T38	20		T39	8		T40	217
all_pins[7]	transitions[0x1=>0x0]	313397	1			T38	26		T39	8		T40	110
all_pins[8]	values[0x0]	857442	1			T33	1		T34	1		T35	1
all_pins[8]	values[0x1]	521459	1			T38	33		T39	18		T40	359
all_pins[8]	transitions[0x0=>0x1]	311981	1			T38	23		T39	10		T40	197
all_pins[8]	transitions[0x1=>0x0]	310741	1			T38	19		T39	8		T40	133
all_pins[9]	values[0x0]	855563	1			T33	1		T34	1		T35	1
all_pins[9]	values[0x1]	523338	1			T38	35		T39	14		T40	335
all_pins[9]	transitions[0x0=>0x1]	312313	1			T38	24		T39	6		T40	157
all_pins[9]	transitions[0x1=>0x0]	310434	1			T38	22		T39	10		T40	181
all_pins[10]	values[0x0]	857843	1			T33	1		T34	1		T35	1
all_pins[10]	values[0x1]	521058	1			T38	18		T39	12		T40	308
all_pins[10]	transitions[0x0=>0x1]	311233	1			T38	14		T39	8		T40	132
all_pins[10]	transitions[0x1=>0x0]	313513	1			T38	31		T39	10		T40	159
all_pins[11]	values[0x0]	858232	1			T33	1		T34	1		T35	1
all_pins[11]	values[0x1]	520669	1			T38	50		T39	18		T40	294
all_pins[11]	transitions[0x0=>0x1]	311063	1			T38	42		T39	9		T40	129
all_pins[11]	transitions[0x1=>0x0]	311452	1			T38	10		T39	3		T40	143
all_pins[12]	values[0x0]	856152	1			T33	1		T34	1		T35	1
all_pins[12]	values[0x1]	522749	1			T38	46		T39	13		T40	257
all_pins[12]	transitions[0x0=>0x1]	312808	1			T38	24		T39	6		T40	205
all_pins[12]	transitions[0x1=>0x0]	310728	1			T38	28		T39	11		T40	242
all_pins[13]	values[0x0]	860113	1			T33	1		T34	1		T35	1
all_pins[13]	values[0x1]	518788	1			T38	24		T39	24		T40	187
all_pins[13]	transitions[0x0=>0x1]	310467	1			T38	13		T39	14		T40	110
all_pins[13]	transitions[0x1=>0x0]	314428	1			T38	35		T39	3		T40	180
all_pins[14]	values[0x0]	857665	1			T33	1		T34	1		T35	1
all_pins[14]	values[0x1]	521236	1			T38	46		T39	18		T40	236
all_pins[14]	transitions[0x0=>0x1]	312450	1			T38	31		T39	3		T40	187
all_pins[14]	transitions[0x1=>0x0]	310002	1			T38	9		T39	9		T40	138
all_pins[15]	values[0x0]	857192	1			T33	1		T34	1		T35	1
all_pins[15]	values[0x1]	521709	1			T38	42		T39	11		T40	297
all_pins[15]	transitions[0x0=>0x1]	313608	1			T38	18		T39	4		T40	174
all_pins[15]	transitions[0x1=>0x0]	313135	1			T38	22		T39	11		T40	113
all_pins[16]	values[0x0]	858956	1			T33	1		T34	1		T35	1
all_pins[16]	values[0x1]	519945	1			T38	39		T39	14		T40	313
all_pins[16]	transitions[0x0=>0x1]	310171	1			T38	28		T39	7		T40	156
all_pins[16]	transitions[0x1=>0x0]	311935	1			T38	31		T39	4		T40	140
all_pins[17]	values[0x0]	859099	1			T33	1		T34	1		T35	1
all_pins[17]	values[0x1]	519802	1			T38	35		T39	15		T40	230
all_pins[17]	transitions[0x0=>0x1]	311440	1			T38	22		T39	3		T40	140
all_pins[17]	transitions[0x1=>0x0]	311583	1			T38	26		T39	2		T40	223
all_pins[18]	values[0x0]	858655	1			T33	1		T34	1		T35	1
all_pins[18]	values[0x1]	520246	1			T38	28		T39	11		T40	210
all_pins[18]	transitions[0x0=>0x1]	313814	1			T38	9		T39	4		T40	139
all_pins[18]	transitions[0x1=>0x0]	313370	1			T38	16		T39	8		T40	159
all_pins[19]	values[0x0]	856796	1			T33	1		T34	1		T35	1
all_pins[19]	values[0x1]	522105	1			T38	54		T39	14		T40	281
all_pins[19]	transitions[0x0=>0x1]	313634	1			T38	41		T39	11		T40	171
all_pins[19]	transitions[0x1=>0x0]	311775	1			T38	15		T39	8		T40	100
all_pins[20]	values[0x0]	856229	1			T33	1		T34	1		T35	1
all_pins[20]	values[0x1]	522672	1			T38	43		T39	18		T40	275
all_pins[20]	transitions[0x0=>0x1]	312941	1			T38	18		T39	8		T40	157
all_pins[20]	transitions[0x1=>0x0]	312374	1			T38	29		T39	4		T40	163
all_pins[21]	values[0x0]	856848	1			T33	1		T34	1		T35	1
all_pins[21]	values[0x1]	522053	1			T38	27		T39	13		T40	215
all_pins[21]	transitions[0x0=>0x1]	313122	1			T38	5		T39	5		T40	101
all_pins[21]	transitions[0x1=>0x0]	313741	1			T38	21		T39	10		T40	161
all_pins[22]	values[0x0]	858750	1			T33	1		T34	1		T35	1
all_pins[22]	values[0x1]	520151	1			T38	45		T39	16		T40	321
all_pins[22]	transitions[0x0=>0x1]	310645	1			T38	33		T39	10		T40	201
all_pins[22]	transitions[0x1=>0x0]	312547	1			T38	15		T39	7		T40	95
all_pins[23]	values[0x0]	859282	1			T33	1		T34	1		T35	1
all_pins[23]	values[0x1]	519619	1			T38	60		T39	20		T40	276
all_pins[23]	transitions[0x0=>0x1]	311094	1			T38	28		T39	12		T40	156
all_pins[23]	transitions[0x1=>0x0]	311626	1			T38	13		T39	8		T40	201
all_pins[24]	values[0x0]	855738	1			T33	1		T34	1		T35	1
all_pins[24]	values[0x1]	523163	1			T38	38		T39	22		T40	218
all_pins[24]	transitions[0x0=>0x1]	313290	1			T38	14		T39	7		T40	139
all_pins[24]	transitions[0x1=>0x0]	309746	1			T38	36		T39	5		T40	197
all_pins[25]	values[0x0]	857083	1			T33	1		T34	1		T35	1
all_pins[25]	values[0x1]	521818	1			T38	40		T39	17		T40	290
all_pins[25]	transitions[0x0=>0x1]	309964	1			T38	22		T39	6		T40	176
all_pins[25]	transitions[0x1=>0x0]	311309	1			T38	20		T39	11		T40	104
all_pins[26]	values[0x0]	858067	1			T33	1		T34	1		T35	1
all_pins[26]	values[0x1]	520834	1			T38	39		T39	8		T40	330
all_pins[26]	transitions[0x0=>0x1]	312908	1			T38	19		T39	7		T40	219
all_pins[26]	transitions[0x1=>0x0]	313892	1			T38	20		T39	16		T40	179
all_pins[27]	values[0x0]	855003	1			T33	1		T34	1		T35	1
all_pins[27]	values[0x1]	523898	1			T38	20		T39	15		T40	244
all_pins[27]	transitions[0x0=>0x1]	313619	1			T38	18		T39	11		T40	119
all_pins[27]	transitions[0x1=>0x0]	310555	1			T38	37		T39	4		T40	205
all_pins[28]	values[0x0]	858060	1			T33	1		T34	1		T35	1
all_pins[28]	values[0x1]	520841	1			T38	39		T39	12		T40	289
all_pins[28]	transitions[0x0=>0x1]	312552	1			T38	35		T39	8		T40	189
all_pins[28]	transitions[0x1=>0x0]	315609	1			T38	16		T39	11		T40	144
all_pins[29]	values[0x0]	855564	1			T33	1		T34	1		T35	1
all_pins[29]	values[0x1]	523337	1			T38	35		T39	17		T40	273
all_pins[29]	transitions[0x0=>0x1]	314609	1			T38	21		T39	9		T40	137
all_pins[29]	transitions[0x1=>0x0]	312113	1			T38	25		T39	4		T40	153
all_pins[30]	values[0x0]	855511	1			T33	1		T34	1		T35	1
all_pins[30]	values[0x1]	523390	1			T38	43		T39	14		T40	258
all_pins[30]	transitions[0x0=>0x1]	312506	1			T38	27		T39	7		T40	132
all_pins[30]	transitions[0x1=>0x0]	312453	1			T38	19		T39	10		T40	147
all_pins[31]	values[0x0]	858565	1			T33	1		T34	1		T35	1
all_pins[31]	values[0x1]	520336	1			T38	6		T39	10		T40	248
all_pins[31]	transitions[0x0=>0x1]	310727	1			T39	8		T40	148		T41	30
all_pins[31]	transitions[0x1=>0x0]	313781	1			T38	37		T39	12		T40	158