Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	5983728	1			T33	340		T34	526		T35	292
all_values[1]	5983728	1			T33	340		T34	526		T35	292
all_values[2]	5983728	1			T33	340		T34	526		T35	292
all_values[3]	5983728	1			T33	340		T34	526		T35	292
all_values[4]	5983728	1			T33	340		T34	526		T35	292
all_values[5]	5983728	1			T33	340		T34	526		T35	292
all_values[6]	5983728	1			T33	340		T34	526		T35	292
all_values[7]	5983728	1			T33	340		T34	526		T35	292
all_values[8]	5983728	1			T33	340		T34	526		T35	292
all_values[9]	5983728	1			T33	340		T34	526		T35	292
all_values[10]	5983728	1			T33	340		T34	526		T35	292
all_values[11]	5983728	1			T33	340		T34	526		T35	292
all_values[12]	5983728	1			T33	340		T34	526		T35	292
all_values[13]	5983728	1			T33	340		T34	526		T35	292
all_values[14]	5983728	1			T33	340		T34	526		T35	292
all_values[15]	5983728	1			T33	340		T34	526		T35	292
all_values[16]	5983728	1			T33	340		T34	526		T35	292
all_values[17]	5983728	1			T33	340		T34	526		T35	292
all_values[18]	5983728	1			T33	340		T34	526		T35	292
all_values[19]	5983728	1			T33	340		T34	526		T35	292
all_values[20]	5983728	1			T33	340		T34	526		T35	292
all_values[21]	5983728	1			T33	340		T34	526		T35	292
all_values[22]	5983728	1			T33	340		T34	526		T35	292
all_values[23]	5983728	1			T33	340		T34	526		T35	292
all_values[24]	5983728	1			T33	340		T34	526		T35	292
all_values[25]	5983728	1			T33	340		T34	526		T35	292
all_values[26]	5983728	1			T33	340		T34	526		T35	292
all_values[27]	5983728	1			T33	340		T34	526		T35	292
all_values[28]	5983728	1			T33	340		T34	526		T35	292
all_values[29]	5983728	1			T33	340		T34	526		T35	292
all_values[30]	5983728	1			T33	340		T34	526		T35	292
all_values[31]	5983728	1			T33	340		T34	526		T35	292

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

132253894

1

T33

10880

T34

16832

T35

9344

auto[1]

59225402

1

T38

3093

T40

34643

T41

7489

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

84728562

1

T33

10880

T34

16832

T35

9344

auto[1]

106750734

1

T38

5344

T40

63267

T41

12568

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

189874045

1

T33

10880

T34

16832

T35

9344

auto[1]

1605251

1

T41

447

T22

220

T53

81

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	2459070	1			T33	340		T34	526		T35	292
all_values[0]	auto[0]	auto[0]	auto[1]	1649733	1			T38	92		T40	598		T41	117
all_values[0]	auto[0]	auto[1]	auto[0]	183720	1			T38	10		T40	154		T41	57
all_values[0]	auto[0]	auto[1]	auto[1]	1641079	1			T38	75		T40	1304		T41	262
all_values[0]	auto[1]	auto[0]	auto[1]	25184	1			T41	1		T22	4		T53	1
all_values[0]	auto[1]	auto[1]	auto[1]	24942	1			T41	10		T22	3		T53	1
all_values[1]	auto[0]	auto[0]	auto[0]	2458667	1			T33	340		T34	526		T35	292
all_values[1]	auto[0]	auto[0]	auto[1]	1657292	1			T38	87		T40	776		T41	101
all_values[1]	auto[0]	auto[1]	auto[0]	189908	1			T38	12		T40	94		T41	55
all_values[1]	auto[0]	auto[1]	auto[1]	1627651	1			T38	81		T40	1231		T41	271
all_values[1]	auto[1]	auto[0]	auto[1]	25141	1			T41	4		T22	5		T53	1
all_values[1]	auto[1]	auto[1]	auto[1]	25069	1			T41	12		T22	2		T53	1
all_values[2]	auto[0]	auto[0]	auto[0]	2457254	1			T33	340		T34	526		T35	292
all_values[2]	auto[0]	auto[0]	auto[1]	1650515	1			T38	84		T40	1381		T41	73
all_values[2]	auto[0]	auto[1]	auto[0]	192344	1			T38	15		T40	52		T41	76
all_values[2]	auto[0]	auto[1]	auto[1]	1633460	1			T38	79		T40	657		T41	301
all_values[2]	auto[1]	auto[0]	auto[1]	25421	1			T41	3		T22	1		T42	11
all_values[2]	auto[1]	auto[1]	auto[1]	24734	1			T41	10		T22	4		T42	25
all_values[3]	auto[0]	auto[0]	auto[0]	2458551	1			T33	340		T34	526		T35	292
all_values[3]	auto[0]	auto[0]	auto[1]	1643673	1			T38	58		T40	796		T41	167
all_values[3]	auto[0]	auto[1]	auto[0]	190392	1			T38	20		T40	80		T41	40
all_values[3]	auto[0]	auto[1]	auto[1]	1640956	1			T38	100		T40	1189		T41	186
all_values[3]	auto[1]	auto[0]	auto[1]	25038	1			T41	9		T22	5		T53	3
all_values[3]	auto[1]	auto[1]	auto[1]	25118	1			T41	7		T22	3		T53	1
all_values[4]	auto[0]	auto[0]	auto[0]	2459503	1			T33	340		T34	526		T35	292
all_values[4]	auto[0]	auto[0]	auto[1]	1639190	1			T38	69		T40	985		T41	172
all_values[4]	auto[0]	auto[1]	auto[0]	188762	1			T38	25		T40	63		T41	33
all_values[4]	auto[0]	auto[1]	auto[1]	1646202	1			T38	93		T40	1009		T41	209
all_values[4]	auto[1]	auto[0]	auto[1]	24918	1			T41	11		T22	4		T53	1
all_values[4]	auto[1]	auto[1]	auto[1]	25153	1			T41	7		T22	5		T53	1
all_values[5]	auto[0]	auto[0]	auto[0]	2457400	1			T33	340		T34	526		T35	292
all_values[5]	auto[0]	auto[0]	auto[1]	1647319	1			T38	63		T40	1036		T41	183
all_values[5]	auto[0]	auto[1]	auto[0]	187994	1			T38	15		T40	65		T41	75
all_values[5]	auto[0]	auto[1]	auto[1]	1640895	1			T38	82		T40	939		T41	153
all_values[5]	auto[1]	auto[0]	auto[1]	25188	1			T41	8		T22	6		T42	26
all_values[5]	auto[1]	auto[1]	auto[1]	24932	1			T41	4		T22	1		T53	1
all_values[6]	auto[0]	auto[0]	auto[0]	2456790	1			T33	340		T34	526		T35	292
all_values[6]	auto[0]	auto[0]	auto[1]	1649712	1			T38	104		T40	1336		T41	100
all_values[6]	auto[0]	auto[1]	auto[0]	187297	1			T38	12		T40	32		T41	46
all_values[6]	auto[0]	auto[1]	auto[1]	1639673	1			T38	73		T40	664		T41	234
all_values[6]	auto[1]	auto[0]	auto[1]	25305	1			T41	7		T22	3		T53	2
all_values[6]	auto[1]	auto[1]	auto[1]	24951	1			T41	11		T22	2		T53	2
all_values[7]	auto[0]	auto[0]	auto[0]	2459482	1			T33	340		T34	526		T35	292
all_values[7]	auto[0]	auto[0]	auto[1]	1651654	1			T38	123		T40	902		T41	187
all_values[7]	auto[0]	auto[1]	auto[0]	186027	1			T38	1		T40	127		T41	24
all_values[7]	auto[0]	auto[1]	auto[1]	1636413	1			T38	60		T40	1063		T41	217
all_values[7]	auto[1]	auto[0]	auto[1]	25271	1			T41	8		T22	1		T53	1
all_values[7]	auto[1]	auto[1]	auto[1]	24881	1			T41	9		T22	3		T53	1
all_values[8]	auto[0]	auto[0]	auto[0]	2461458	1			T33	340		T34	526		T35	292
all_values[8]	auto[0]	auto[0]	auto[1]	1648716	1			T38	84		T40	791		T41	221
all_values[8]	auto[0]	auto[1]	auto[0]	190537	1			T38	19		T40	133		T41	48
all_values[8]	auto[0]	auto[1]	auto[1]	1632796	1			T38	77		T40	1192		T41	147
all_values[8]	auto[1]	auto[0]	auto[1]	25143	1			T41	8		T22	4		T53	1
all_values[8]	auto[1]	auto[1]	auto[1]	25078	1			T41	4		T22	3		T53	2
all_values[9]	auto[0]	auto[0]	auto[0]	2461061	1			T33	340		T34	526		T35	292
all_values[9]	auto[0]	auto[0]	auto[1]	1634780	1			T38	86		T40	889		T41	249
all_values[9]	auto[0]	auto[1]	auto[0]	190479	1			T38	22		T40	55		T41	26
all_values[9]	auto[0]	auto[1]	auto[1]	1647329	1			T38	77		T40	1144		T41	139
all_values[9]	auto[1]	auto[0]	auto[1]	25045	1			T41	8		T22	8		T53	1
all_values[9]	auto[1]	auto[1]	auto[1]	25034	1			T41	3		T22	3		T42	18
all_values[10]	auto[0]	auto[0]	auto[0]	2461836	1			T33	340		T34	526		T35	292
all_values[10]	auto[0]	auto[0]	auto[1]	1645151	1			T38	94		T40	905		T41	203
all_values[10]	auto[0]	auto[1]	auto[0]	191208	1			T38	22		T40	83		T41	28
all_values[10]	auto[0]	auto[1]	auto[1]	1635373	1			T38	49		T40	1116		T41	154
all_values[10]	auto[1]	auto[0]	auto[1]	25287	1			T41	11		T22	2		T53	3
all_values[10]	auto[1]	auto[1]	auto[1]	24873	1			T41	5		T22	4		T42	22
all_values[11]	auto[0]	auto[0]	auto[0]	2460326	1			T33	340		T34	526		T35	292
all_values[11]	auto[0]	auto[0]	auto[1]	1649972	1			T38	91		T40	949		T41	258
all_values[11]	auto[0]	auto[1]	auto[0]	189367	1			T38	6		T40	113		T41	20
all_values[11]	auto[0]	auto[1]	auto[1]	1634003	1			T38	96		T40	1048		T41	163
all_values[11]	auto[1]	auto[0]	auto[1]	24989	1			T41	11		T22	4		T53	1
all_values[11]	auto[1]	auto[1]	auto[1]	25071	1			T41	5		T22	1		T42	20
all_values[12]	auto[0]	auto[0]	auto[0]	2456255	1			T33	340		T34	526		T35	292
all_values[12]	auto[0]	auto[0]	auto[1]	1647128	1			T38	92		T40	929		T41	311
all_values[12]	auto[0]	auto[1]	auto[0]	187351	1			T38	2		T40	115		T41	19
all_values[12]	auto[0]	auto[1]	auto[1]	1642922	1			T38	96		T40	980		T41	101
all_values[12]	auto[1]	auto[0]	auto[1]	25187	1			T41	9		T22	3		T53	1
all_values[12]	auto[1]	auto[1]	auto[1]	24885	1			T41	4		T22	4		T53	1
all_values[13]	auto[0]	auto[0]	auto[0]	2461270	1			T33	340		T34	526		T35	292
all_values[13]	auto[0]	auto[0]	auto[1]	1650515	1			T38	86		T40	1301		T41	210
all_values[13]	auto[0]	auto[1]	auto[0]	191931	1			T38	29		T40	51		T41	27
all_values[13]	auto[0]	auto[1]	auto[1]	1629892	1			T38	61		T40	704		T41	200
all_values[13]	auto[1]	auto[0]	auto[1]	25513	1			T41	5		T22	3		T53	1
all_values[13]	auto[1]	auto[1]	auto[1]	24607	1			T41	6		T22	2		T42	22
all_values[14]	auto[0]	auto[0]	auto[0]	2458420	1			T33	340		T34	526		T35	292
all_values[14]	auto[0]	auto[0]	auto[1]	1654492	1			T38	80		T40	1003		T41	153
all_values[14]	auto[0]	auto[1]	auto[0]	187445	1			T38	6		T40	103		T41	53
all_values[14]	auto[0]	auto[1]	auto[1]	1633517	1			T38	104		T40	940		T41	206
all_values[14]	auto[1]	auto[0]	auto[1]	25162	1			T41	6		T22	5		T53	2
all_values[14]	auto[1]	auto[1]	auto[1]	24692	1			T41	9		T22	2		T42	17
all_values[15]	auto[0]	auto[0]	auto[0]	2459678	1			T33	340		T34	526		T35	292
all_values[15]	auto[0]	auto[0]	auto[1]	1651269	1			T38	81		T40	794		T41	161
all_values[15]	auto[0]	auto[1]	auto[0]	189496	1			T38	11		T40	121		T41	22
all_values[15]	auto[0]	auto[1]	auto[1]	1632938	1			T38	96		T40	1176		T41	211
all_values[15]	auto[1]	auto[0]	auto[1]	25461	1			T41	6		T22	3		T53	1
all_values[15]	auto[1]	auto[1]	auto[1]	24886	1			T41	11		T22	3		T53	1
all_values[16]	auto[0]	auto[0]	auto[0]	2461082	1			T33	340		T34	526		T35	292
all_values[16]	auto[0]	auto[0]	auto[1]	1652658	1			T38	86		T40	834		T41	280
all_values[16]	auto[0]	auto[1]	auto[0]	187382	1			T38	16		T40	74		T41	25
all_values[16]	auto[0]	auto[1]	auto[1]	1632568	1			T38	91		T40	1142		T41	71
all_values[16]	auto[1]	auto[0]	auto[1]	25305	1			T41	11		T22	5		T53	1
all_values[16]	auto[1]	auto[1]	auto[1]	24733	1			T41	3		T22	3		T53	2
all_values[17]	auto[0]	auto[0]	auto[0]	2458207	1			T33	340		T34	526		T35	292
all_values[17]	auto[0]	auto[0]	auto[1]	1640245	1			T38	115		T40	1185		T41	197
all_values[17]	auto[0]	auto[1]	auto[0]	186119	1			T40	49		T41	25		T22	29
all_values[17]	auto[0]	auto[1]	auto[1]	1648962	1			T38	76		T40	849		T41	129
all_values[17]	auto[1]	auto[0]	auto[1]	25223	1			T41	10		T22	2		T53	3
all_values[17]	auto[1]	auto[1]	auto[1]	24972	1			T41	6		T22	2		T42	19
all_values[18]	auto[0]	auto[0]	auto[0]	2463886	1			T33	340		T34	526		T35	292
all_values[18]	auto[0]	auto[0]	auto[1]	1649424	1			T38	91		T40	1109		T41	226
all_values[18]	auto[0]	auto[1]	auto[0]	184090	1			T38	12		T40	103		T41	58
all_values[18]	auto[0]	auto[1]	auto[1]	1636137	1			T38	72		T40	794		T41	145
all_values[18]	auto[1]	auto[0]	auto[1]	25589	1			T41	4		T22	7		T53	2
all_values[18]	auto[1]	auto[1]	auto[1]	24602	1			T41	8		T22	3		T53	1
all_values[19]	auto[0]	auto[0]	auto[0]	2456274	1			T33	340		T34	526		T35	292
all_values[19]	auto[0]	auto[0]	auto[1]	1651341	1			T38	51		T40	1032		T41	207
all_values[19]	auto[0]	auto[1]	auto[0]	183074	1			T38	18		T40	51		T41	24
all_values[19]	auto[0]	auto[1]	auto[1]	1642911	1			T38	124		T40	965		T41	159
all_values[19]	auto[1]	auto[0]	auto[1]	25539	1			T41	9		T22	7		T42	20
all_values[19]	auto[1]	auto[1]	auto[1]	24589	1			T41	3		T22	1		T53	1
all_values[20]	auto[0]	auto[0]	auto[0]	2458888	1			T33	340		T34	526		T35	292
all_values[20]	auto[0]	auto[0]	auto[1]	1645348	1			T38	80		T40	924		T41	201
all_values[20]	auto[0]	auto[1]	auto[0]	188746	1			T38	2		T40	85		T41	13
all_values[20]	auto[0]	auto[1]	auto[1]	1640593	1			T38	108		T40	1067		T41	222
all_values[20]	auto[1]	auto[0]	auto[1]	25225	1			T41	3		T22	4		T53	2
all_values[20]	auto[1]	auto[1]	auto[1]	24928	1			T41	7		T22	1		T53	1
all_values[21]	auto[0]	auto[0]	auto[0]	2460695	1			T33	340		T34	526		T35	292
all_values[21]	auto[0]	auto[0]	auto[1]	1642194	1			T38	89		T40	1043		T41	189
all_values[21]	auto[0]	auto[1]	auto[0]	188615	1			T38	18		T40	131		T41	41
all_values[21]	auto[0]	auto[1]	auto[1]	1642133	1			T38	76		T40	824		T41	122
all_values[21]	auto[1]	auto[0]	auto[1]	25261	1			T41	7		T22	7		T53	3
all_values[21]	auto[1]	auto[1]	auto[1]	24830	1			T41	7		T22	1		T53	2
all_values[22]	auto[0]	auto[0]	auto[0]	2458682	1			T33	340		T34	526		T35	292
all_values[22]	auto[0]	auto[0]	auto[1]	1649684	1			T38	68		T40	895		T41	221
all_values[22]	auto[0]	auto[1]	auto[0]	183949	1			T38	10		T40	67		T41	56
all_values[22]	auto[0]	auto[1]	auto[1]	1641078	1			T38	97		T40	1143		T41	149
all_values[22]	auto[1]	auto[0]	auto[1]	25740	1			T41	9		T22	2		T53	4
all_values[22]	auto[1]	auto[1]	auto[1]	24595	1			T41	6		T22	4		T42	28
all_values[23]	auto[0]	auto[0]	auto[0]	2463224	1			T33	340		T34	526		T35	292
all_values[23]	auto[0]	auto[0]	auto[1]	1659178	1			T38	51		T40	1026		T41	213
all_values[23]	auto[0]	auto[1]	auto[0]	188613	1			T38	6		T40	80		T41	20
all_values[23]	auto[0]	auto[1]	auto[1]	1622620	1			T38	129		T40	954		T41	208
all_values[23]	auto[1]	auto[0]	auto[1]	25487	1			T41	7		T22	3		T53	1
all_values[23]	auto[1]	auto[1]	auto[1]	24606	1			T41	7		T22	6		T53	1
all_values[24]	auto[0]	auto[0]	auto[0]	2461331	1			T33	340		T34	526		T35	292
all_values[24]	auto[0]	auto[0]	auto[1]	1638913	1			T38	56		T40	1154		T41	116
all_values[24]	auto[0]	auto[1]	auto[0]	188214	1			T38	17		T40	36		T41	39
all_values[24]	auto[0]	auto[1]	auto[1]	1644886	1			T38	99		T40	854		T41	286
all_values[24]	auto[1]	auto[0]	auto[1]	25336	1			T41	5		T22	5		T53	3
all_values[24]	auto[1]	auto[1]	auto[1]	25048	1			T41	11		T22	2		T42	21
all_values[25]	auto[0]	auto[0]	auto[0]	2457258	1			T33	340		T34	526		T35	292
all_values[25]	auto[0]	auto[0]	auto[1]	1647297	1			T38	92		T40	911		T41	199
all_values[25]	auto[0]	auto[1]	auto[0]	191486	1			T38	15		T40	62		T41	3
all_values[25]	auto[0]	auto[1]	auto[1]	1637399	1			T38	75		T40	1116		T41	237
all_values[25]	auto[1]	auto[0]	auto[1]	25304	1			T41	8		T22	4		T53	2
all_values[25]	auto[1]	auto[1]	auto[1]	24984	1			T41	7		T22	2		T53	1
all_values[26]	auto[0]	auto[0]	auto[0]	2458365	1			T33	340		T34	526		T35	292
all_values[26]	auto[0]	auto[0]	auto[1]	1649555	1			T38	108		T40	695		T41	171
all_values[26]	auto[0]	auto[1]	auto[0]	189011	1			T38	7		T40	141		T41	15
all_values[26]	auto[0]	auto[1]	auto[1]	1636944	1			T38	69		T40	1242		T41	262
all_values[26]	auto[1]	auto[0]	auto[1]	25392	1			T41	6		T22	3		T53	1
all_values[26]	auto[1]	auto[1]	auto[1]	24461	1			T41	5		T22	3		T53	1
all_values[27]	auto[0]	auto[0]	auto[0]	2457679	1			T33	340		T34	526		T35	292
all_values[27]	auto[0]	auto[0]	auto[1]	1649406	1			T38	101		T40	1079		T41	176
all_values[27]	auto[0]	auto[1]	auto[0]	182770	1			T38	19		T40	46		T41	35
all_values[27]	auto[0]	auto[1]	auto[1]	1643792	1			T38	39		T40	875		T41	217
all_values[27]	auto[1]	auto[0]	auto[1]	25107	1			T41	8		T22	1		T53	2
all_values[27]	auto[1]	auto[1]	auto[1]	24974	1			T41	7		T22	3		T42	21
all_values[28]	auto[0]	auto[0]	auto[0]	2462589	1			T33	340		T34	526		T35	292
all_values[28]	auto[0]	auto[0]	auto[1]	1653498	1			T38	83		T40	947		T41	247
all_values[28]	auto[0]	auto[1]	auto[0]	186768	1			T38	6		T40	83		T41	46
all_values[28]	auto[0]	auto[1]	auto[1]	1630325	1			T38	88		T40	1046		T41	138
all_values[28]	auto[1]	auto[0]	auto[1]	25747	1			T41	5		T22	7		T53	4
all_values[28]	auto[1]	auto[1]	auto[1]	24801	1			T41	6		T22	3		T42	22
all_values[29]	auto[0]	auto[0]	auto[0]	2461649	1			T33	340		T34	526		T35	292
all_values[29]	auto[0]	auto[0]	auto[1]	1632936	1			T38	71		T40	978		T41	275
all_values[29]	auto[0]	auto[1]	auto[0]	191398	1			T38	29		T40	121		T41	40
all_values[29]	auto[0]	auto[1]	auto[1]	1647457	1			T38	79		T40	958		T41	117
all_values[29]	auto[1]	auto[0]	auto[1]	25597	1			T41	9		T22	2		T53	4
all_values[29]	auto[1]	auto[1]	auto[1]	24691	1			T41	3		T22	7		T53	1
all_values[30]	auto[0]	auto[0]	auto[0]	2464486	1			T33	340		T34	526		T35	292
all_values[30]	auto[0]	auto[0]	auto[1]	1651726	1			T38	47		T40	1025		T41	140
all_values[30]	auto[0]	auto[1]	auto[0]	186667	1			T38	28		T40	115		T41	47
all_values[30]	auto[0]	auto[1]	auto[1]	1630829	1			T38	107		T40	855		T41	229
all_values[30]	auto[1]	auto[0]	auto[1]	25049	1			T41	5		T22	3		T53	3
all_values[30]	auto[1]	auto[1]	auto[1]	24971	1			T41	9		T22	2		T42	11
all_values[31]	auto[0]	auto[0]	auto[0]	2458019	1			T33	340		T34	526		T35	292
all_values[31]	auto[0]	auto[0]	auto[1]	1650388	1			T38	131		T40	1139		T41	90
all_values[31]	auto[0]	auto[1]	auto[0]	188067	1			T38	13		T40	38		T41	25
all_values[31]	auto[0]	auto[1]	auto[1]	1636848	1			T38	22		T40	880		T41	262
all_values[31]	auto[1]	auto[0]	auto[1]	25503	1			T41	5		T22	5		T53	2
all_values[31]	auto[1]	auto[1]	auto[1]	24903	1			T41	9		T22	4		T53	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal