Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	5942481	1			T33	622		T34	882		T35	576
bins_for_gpio_bits[1]	5942481	1			T33	622		T34	882		T35	576
bins_for_gpio_bits[2]	5942481	1			T33	622		T34	882		T35	576
bins_for_gpio_bits[3]	5942481	1			T33	622		T34	882		T35	576
bins_for_gpio_bits[4]	5942481	1			T33	622		T34	882		T35	576
bins_for_gpio_bits[5]	5942481	1			T33	622		T34	882		T35	576
bins_for_gpio_bits[6]	5942481	1			T33	622		T34	882		T35	576
bins_for_gpio_bits[7]	5942481	1			T33	622		T34	882		T35	576
bins_for_gpio_bits[8]	5942481	1			T33	622		T34	882		T35	576
bins_for_gpio_bits[9]	5942481	1			T33	622		T34	882		T35	576
bins_for_gpio_bits[10]	5942481	1			T33	622		T34	882		T35	576
bins_for_gpio_bits[11]	5942481	1			T33	622		T34	882		T35	576
bins_for_gpio_bits[12]	5942481	1			T33	622		T34	882		T35	576
bins_for_gpio_bits[13]	5942481	1			T33	622		T34	882		T35	576
bins_for_gpio_bits[14]	5942481	1			T33	622		T34	882		T35	576
bins_for_gpio_bits[15]	5942481	1			T33	622		T34	882		T35	576
bins_for_gpio_bits[16]	5942481	1			T33	622		T34	882		T35	576
bins_for_gpio_bits[17]	5942481	1			T33	622		T34	882		T35	576
bins_for_gpio_bits[18]	5942481	1			T33	622		T34	882		T35	576
bins_for_gpio_bits[19]	5942481	1			T33	622		T34	882		T35	576
bins_for_gpio_bits[20]	5942481	1			T33	622		T34	882		T35	576
bins_for_gpio_bits[21]	5942481	1			T33	622		T34	882		T35	576
bins_for_gpio_bits[22]	5942481	1			T33	622		T34	882		T35	576
bins_for_gpio_bits[23]	5942481	1			T33	622		T34	882		T35	576
bins_for_gpio_bits[24]	5942481	1			T33	622		T34	882		T35	576
bins_for_gpio_bits[25]	5942481	1			T33	622		T34	882		T35	576
bins_for_gpio_bits[26]	5942481	1			T33	622		T34	882		T35	576
bins_for_gpio_bits[27]	5942481	1			T33	622		T34	882		T35	576
bins_for_gpio_bits[28]	5942481	1			T33	622		T34	882		T35	576
bins_for_gpio_bits[29]	5942481	1			T33	622		T34	882		T35	576
bins_for_gpio_bits[30]	5942481	1			T33	622		T34	882		T35	576
bins_for_gpio_bits[31]	5942481	1			T33	622		T34	882		T35	576

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

95007520

1

T33

14353

T34

19711

T35

4225

auto[1]

95151872

1

T33

5551

T34

8513

T35

14207

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

160533416

1

T33

10901

T34

16658

T35

13973

auto[1]

29625976

1

T33

9003

T34

11566

T35

4459

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

151907113

1

T33

10954

T34

16866

T35

9682

auto[1]

38252279

1

T33

8950

T34

11358

T35

8750

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	2135313	1			T33	184		T34	232		T35	34
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	2145475	1			T33	31		T34	87		T35	183
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	462976	1			T33	176		T34	216		T35	104
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	367481	1			T33	98		T34	135		T35	24
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	367685	1			T35	155		T36	35		T41	109
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	463551	1			T33	133		T34	212		T35	76
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	2134035	1			T33	170		T34	256		T35	35
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	2151341	1			T33	35		T34	85		T35	223
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	467248	1			T33	142		T34	197		T35	69
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	363648	1			T33	133		T34	180		T35	21
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	365771	1			T35	165		T36	28		T37	55
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	460438	1			T33	142		T34	164		T35	63
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	2129413	1			T33	160		T34	249		T35	30
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	2153658	1			T33	35		T34	90		T35	223
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	466234	1			T33	148		T34	208		T35	95
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	365486	1			T33	110		T34	163		T35	23
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	367135	1			T35	146		T36	24		T37	20
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	460555	1			T33	169		T34	172		T35	59
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	2135592	1			T33	168		T34	262		T35	35
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	2141147	1			T33	27		T34	87		T35	177
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	466408	1			T33	151		T34	158		T35	63
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	365054	1			T33	122		T34	192		T35	29
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	369876	1			T35	210		T36	52		T37	10
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	464404	1			T33	154		T34	183		T35	62
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	2134124	1			T33	153		T34	255		T35	28
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	2152185	1			T33	32		T34	89		T35	181
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	461453	1			T33	125		T34	186		T35	67
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	363785	1			T33	152		T34	190		T35	22
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	369422	1			T35	216		T36	67		T41	56
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	461512	1			T33	160		T34	162		T35	62
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	2130695	1			T33	172		T34	252		T35	26
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	2148535	1			T33	30		T34	84		T35	150
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	462775	1			T33	144		T34	198		T35	71
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	368026	1			T33	112		T34	134		T35	29
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	370149	1			T35	232		T36	60		T37	20
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	462301	1			T33	164		T34	214		T35	68
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	2144888	1			T33	151		T34	261		T35	45
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	2135267	1			T33	29		T34	88		T35	238
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	465114	1			T33	126		T34	189		T35	51
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	364305	1			T33	134		T34	156		T35	17
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	371525	1			T35	179		T36	21		T37	3
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	461382	1			T33	182		T34	188		T35	46
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	2143353	1			T33	155		T34	223		T35	37
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	2134514	1			T33	28		T34	89		T35	218
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	464396	1			T33	144		T34	178		T35	65
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	368464	1			T33	99		T34	182		T35	29
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	367869	1			T35	176		T36	26		T37	3
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	463885	1			T33	196		T34	210		T35	51
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	2139524	1			T33	170		T34	268		T35	30
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	2142744	1			T33	31		T34	81		T35	208
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	464885	1			T33	122		T34	154		T35	54
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	365042	1			T33	169		T34	180		T35	37
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	368567	1			T35	188		T36	34		T41	80
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	461719	1			T33	130		T34	199		T35	59
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	2145612	1			T33	164		T34	282		T35	42
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	2135184	1			T33	29		T34	91		T35	208
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	466245	1			T33	138		T34	197		T35	75
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	363584	1			T33	153		T34	168		T35	11
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	369557	1			T35	156		T36	26		T37	14
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	462299	1			T33	138		T34	144		T35	84
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	2139474	1			T33	181		T34	221		T35	32
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	2142312	1			T33	31		T34	97		T35	200
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	467928	1			T33	142		T34	204		T35	72
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	363321	1			T33	138		T34	160		T35	29
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	367506	1			T35	173		T36	26		T37	10
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	461940	1			T33	130		T34	200		T35	70
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	2142899	1			T33	172		T34	274		T35	22
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	2138468	1			T33	30		T34	83		T35	188
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	462965	1			T33	136		T34	153		T35	63
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	367151	1			T33	132		T34	188		T35	34
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	369973	1			T35	181		T36	38		T37	20
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	461025	1			T33	152		T34	184		T35	88
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	2139493	1			T33	149		T34	247		T35	27
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	2141286	1			T33	27		T34	85		T35	183
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	465691	1			T33	138		T34	182		T35	91
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	362956	1			T33	150		T34	150		T35	31
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	368423	1			T35	205		T36	46		T41	60
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	464632	1			T33	158		T34	218		T35	39
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	2138651	1			T33	199		T34	280		T35	28
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	2144577	1			T33	27		T34	89		T35	196
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	464665	1			T33	160		T34	186		T35	32
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	365114	1			T33	136		T34	164		T35	24
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	369269	1			T35	239		T36	43		T37	11
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	460205	1			T33	100		T34	163		T35	57
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	2130198	1			T33	162		T34	283		T35	36
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	2151309	1			T33	31		T34	91		T35	205
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	466305	1			T33	129		T34	212		T35	66
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	364993	1			T33	132		T34	112		T35	16
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	368554	1			T35	176		T36	67		T37	55
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	461122	1			T33	168		T34	184		T35	77
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	2149661	1			T33	167		T34	281		T35	28
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	2132636	1			T33	29		T34	76		T35	170
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	467844	1			T33	118		T34	210		T35	103
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	363395	1			T33	142		T34	180		T35	30
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	367835	1			T35	165		T36	39		T37	41
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	461110	1			T33	166		T34	135		T35	80
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	2142033	1			T33	161		T34	274		T35	22
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	2140897	1			T33	35		T34	87		T35	140
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	464278	1			T33	118		T34	210		T35	38
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	366901	1			T33	142		T34	164		T35	47
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	369895	1			T35	236		T36	54		T37	16
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	458477	1			T33	166		T34	147		T35	93
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	2138913	1			T33	168		T34	270		T35	34
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	2141547	1			T33	27		T34	85		T35	248
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	462405	1			T33	143		T34	160		T35	72
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	366253	1			T33	142		T34	210		T35	24
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	373013	1			T35	152		T36	32		T37	10
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	460350	1			T33	142		T34	157		T35	46
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	2126944	1			T33	202		T34	280		T35	29
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	2156100	1			T33	30		T34	99		T35	154
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	466765	1			T33	154		T34	163		T35	49
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	363911	1			T33	118		T34	178		T35	42
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	368793	1			T35	208		T36	50		T37	6
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	459968	1			T33	118		T34	162		T35	94
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	2145279	1			T33	189		T34	291		T35	37
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	2138182	1			T33	28		T34	80		T35	217
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	465697	1			T33	117		T34	148		T35	103
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	362703	1			T33	144		T34	182		T35	27
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	370766	1			T35	118		T36	52		T41	119
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	459854	1			T33	144		T34	181		T35	74
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	2142186	1			T33	192		T34	263		T35	36
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	2137188	1			T33	32		T34	82		T35	221
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	466491	1			T33	138		T34	162		T35	109
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	364869	1			T33	150		T34	181		T35	31
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	372350	1			T35	130		T36	43		T37	43
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	459397	1			T33	110		T34	194		T35	49
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	2142332	1			T33	156		T34	273		T35	23
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	2145058	1			T33	25		T34	91		T35	214
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	465489	1			T33	138		T34	166		T35	71
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	365053	1			T33	136		T34	150		T35	33
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	368608	1			T35	164		T36	30		T37	13
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	455941	1			T33	167		T34	202		T35	71
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	2146399	1			T33	183		T34	253		T35	33
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	2136276	1			T33	32		T34	90		T35	200
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	464989	1			T33	152		T34	184		T35	96
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	365783	1			T33	151		T34	166		T35	30
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	368266	1			T35	157		T36	37		T37	14
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	460768	1			T33	104		T34	189		T35	60
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	2136369	1			T33	190		T34	276		T35	16
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	2146834	1			T33	33		T34	87		T35	188
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	467435	1			T33	108		T34	168		T35	71
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	365013	1			T33	147		T34	206		T35	41
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	366478	1			T35	190		T36	31		T37	30
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	460352	1			T33	144		T34	145		T35	70
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	2132336	1			T33	170		T34	267		T35	25
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	2145124	1			T33	29		T34	78		T35	246
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	464276	1			T33	132		T34	206		T35	59
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	368632	1			T33	130		T34	164		T35	31
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	371515	1			T35	159		T36	38		T37	11
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	460598	1			T33	161		T34	167		T35	56
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	2142900	1			T33	173		T34	260		T35	18
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	2137192	1			T33	24		T34	73		T35	134
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	465858	1			T33	126		T34	130		T35	63
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	366032	1			T33	152		T34	256		T35	41
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	370843	1			T35	222		T36	39		T37	57
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	459656	1			T33	147		T34	163		T35	98
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	2140656	1			T33	170		T34	270		T35	42
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	2146658	1			T33	25		T34	81		T35	237
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	464672	1			T33	136		T34	176		T35	62
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	363474	1			T33	163		T34	155		T35	18
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	368376	1			T35	158		T36	16		T37	30
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	458645	1			T33	128		T34	200		T35	59
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	2136952	1			T33	202		T34	250		T35	35
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	2149052	1			T33	34		T34	86		T35	230
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	466071	1			T33	150		T34	182		T35	50
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	362672	1			T33	122		T34	194		T35	32
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	369942	1			T35	149		T36	36		T37	40
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	457792	1			T33	114		T34	170		T35	80
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	2137795	1			T33	203		T34	250		T35	39
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	2145335	1			T33	30		T34	81		T35	196
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	462994	1			T33	157		T34	200		T35	85
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	366986	1			T33	132		T34	191		T35	27
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	369650	1			T35	171		T36	41		T41	169
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	459721	1			T33	100		T34	160		T35	58
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	2133722	1			T33	176		T34	215		T35	32
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	2148053	1			T33	26		T34	90		T35	254
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	465293	1			T33	124		T34	166		T35	82
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	367144	1			T33	164		T34	208		T35	25
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	368164	1			T35	143		T36	35		T37	32
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	460105	1			T33	132		T34	203		T35	40
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	2135408	1			T33	205		T34	261		T35	42
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	2144013	1			T33	28		T34	83		T35	221
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	463806	1			T33	130		T34	154		T35	87
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	366896	1			T33	117		T34	198		T35	24
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	371729	1			T35	135		T36	55		T37	47
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	460629	1			T33	142		T34	186		T35	67
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	2142662	1			T33	181		T34	246		T35	10
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	2141914	1			T33	32		T34	79		T35	129
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	461590	1			T33	142		T34	194		T35	76
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	366341	1			T33	129		T34	152		T35	44
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	369572	1			T35	228		T36	16		T37	39
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	460402	1			T33	138		T34	211		T35	89

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal