Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	5942481	1			T33	622		T34	882		T35	576
bins_for_gpio_bits[1]	5942481	1			T33	622		T34	882		T35	576
bins_for_gpio_bits[2]	5942481	1			T33	622		T34	882		T35	576
bins_for_gpio_bits[3]	5942481	1			T33	622		T34	882		T35	576
bins_for_gpio_bits[4]	5942481	1			T33	622		T34	882		T35	576
bins_for_gpio_bits[5]	5942481	1			T33	622		T34	882		T35	576
bins_for_gpio_bits[6]	5942481	1			T33	622		T34	882		T35	576
bins_for_gpio_bits[7]	5942481	1			T33	622		T34	882		T35	576
bins_for_gpio_bits[8]	5942481	1			T33	622		T34	882		T35	576
bins_for_gpio_bits[9]	5942481	1			T33	622		T34	882		T35	576
bins_for_gpio_bits[10]	5942481	1			T33	622		T34	882		T35	576
bins_for_gpio_bits[11]	5942481	1			T33	622		T34	882		T35	576
bins_for_gpio_bits[12]	5942481	1			T33	622		T34	882		T35	576
bins_for_gpio_bits[13]	5942481	1			T33	622		T34	882		T35	576
bins_for_gpio_bits[14]	5942481	1			T33	622		T34	882		T35	576
bins_for_gpio_bits[15]	5942481	1			T33	622		T34	882		T35	576
bins_for_gpio_bits[16]	5942481	1			T33	622		T34	882		T35	576
bins_for_gpio_bits[17]	5942481	1			T33	622		T34	882		T35	576
bins_for_gpio_bits[18]	5942481	1			T33	622		T34	882		T35	576
bins_for_gpio_bits[19]	5942481	1			T33	622		T34	882		T35	576
bins_for_gpio_bits[20]	5942481	1			T33	622		T34	882		T35	576
bins_for_gpio_bits[21]	5942481	1			T33	622		T34	882		T35	576
bins_for_gpio_bits[22]	5942481	1			T33	622		T34	882		T35	576
bins_for_gpio_bits[23]	5942481	1			T33	622		T34	882		T35	576
bins_for_gpio_bits[24]	5942481	1			T33	622		T34	882		T35	576
bins_for_gpio_bits[25]	5942481	1			T33	622		T34	882		T35	576
bins_for_gpio_bits[26]	5942481	1			T33	622		T34	882		T35	576
bins_for_gpio_bits[27]	5942481	1			T33	622		T34	882		T35	576
bins_for_gpio_bits[28]	5942481	1			T33	622		T34	882		T35	576
bins_for_gpio_bits[29]	5942481	1			T33	622		T34	882		T35	576
bins_for_gpio_bits[30]	5942481	1			T33	622		T34	882		T35	576
bins_for_gpio_bits[31]	5942481	1			T33	622		T34	882		T35	576

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

95007520

1

T33

14353

T34

19711

T35

4225

auto[1]

95151872

1

T33

5551

T34

8513

T35

14207

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

95001687

1

T33

14348

T34

19698

T35

4231

auto[1]

95157705

1

T33

5556

T34

8526

T35

14201

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	2881432	1			T33	425		T34	543		T35	144
bins_for_gpio_bits[0]	auto[0]	auto[1]	84137	1			T33	32		T34	40		T35	18
bins_for_gpio_bits[0]	auto[1]	auto[0]	84338	1			T33	33		T34	40		T35	18
bins_for_gpio_bits[0]	auto[1]	auto[1]	2892574	1			T33	132		T34	259		T35	396
bins_for_gpio_bits[1]	auto[0]	auto[0]	2880519	1			T33	412		T34	591		T35	112
bins_for_gpio_bits[1]	auto[0]	auto[1]	84238	1			T33	33		T34	42		T35	13
bins_for_gpio_bits[1]	auto[1]	auto[0]	84412	1			T33	33		T34	42		T35	13
bins_for_gpio_bits[1]	auto[1]	auto[1]	2893312	1			T33	144		T34	207		T35	438
bins_for_gpio_bits[2]	auto[0]	auto[0]	2877148	1			T33	379		T34	575		T35	133
bins_for_gpio_bits[2]	auto[0]	auto[1]	83839	1			T33	38		T34	45		T35	15
bins_for_gpio_bits[2]	auto[1]	auto[0]	83985	1			T33	39		T34	45		T35	15
bins_for_gpio_bits[2]	auto[1]	auto[1]	2897509	1			T33	166		T34	217		T35	413
bins_for_gpio_bits[3]	auto[0]	auto[0]	2882739	1			T33	401		T34	569		T35	116
bins_for_gpio_bits[3]	auto[0]	auto[1]	84147	1			T33	40		T34	42		T35	11
bins_for_gpio_bits[3]	auto[1]	auto[0]	84315	1			T33	40		T34	43		T35	11
bins_for_gpio_bits[3]	auto[1]	auto[1]	2891280	1			T33	141		T34	228		T35	438
bins_for_gpio_bits[4]	auto[0]	auto[0]	2875645	1			T33	391		T34	595		T35	107
bins_for_gpio_bits[4]	auto[0]	auto[1]	83554	1			T33	39		T34	36		T35	10
bins_for_gpio_bits[4]	auto[1]	auto[0]	83717	1			T33	39		T34	36		T35	10
bins_for_gpio_bits[4]	auto[1]	auto[1]	2899565	1			T33	153		T34	215		T35	449
bins_for_gpio_bits[5]	auto[0]	auto[0]	2877760	1			T33	389		T34	541		T35	115
bins_for_gpio_bits[5]	auto[0]	auto[1]	83563	1			T33	39		T34	43		T35	12
bins_for_gpio_bits[5]	auto[1]	auto[0]	83736	1			T33	39		T34	43		T35	11
bins_for_gpio_bits[5]	auto[1]	auto[1]	2897422	1			T33	155		T34	255		T35	438
bins_for_gpio_bits[6]	auto[0]	auto[0]	2890428	1			T33	373		T34	564		T35	102
bins_for_gpio_bits[6]	auto[0]	auto[1]	83733	1			T33	38		T34	42		T35	12
bins_for_gpio_bits[6]	auto[1]	auto[0]	83879	1			T33	38		T34	42		T35	11
bins_for_gpio_bits[6]	auto[1]	auto[1]	2884441	1			T33	173		T34	234		T35	451
bins_for_gpio_bits[7]	auto[0]	auto[0]	2891664	1			T33	359		T34	538		T35	120
bins_for_gpio_bits[7]	auto[0]	auto[1]	84348	1			T33	39		T34	45		T35	11
bins_for_gpio_bits[7]	auto[1]	auto[0]	84549	1			T33	39		T34	45		T35	11
bins_for_gpio_bits[7]	auto[1]	auto[1]	2881920	1			T33	185		T34	254		T35	434
bins_for_gpio_bits[8]	auto[0]	auto[0]	2885262	1			T33	430		T34	559		T35	108
bins_for_gpio_bits[8]	auto[0]	auto[1]	84012	1			T33	31		T34	42		T35	13
bins_for_gpio_bits[8]	auto[1]	auto[0]	84189	1			T33	31		T34	43		T35	13
bins_for_gpio_bits[8]	auto[1]	auto[1]	2889018	1			T33	130		T34	238		T35	442
bins_for_gpio_bits[9]	auto[0]	auto[0]	2890952	1			T33	422		T34	608		T35	114
bins_for_gpio_bits[9]	auto[0]	auto[1]	84324	1			T33	33		T34	39		T35	14
bins_for_gpio_bits[9]	auto[1]	auto[0]	84489	1			T33	33		T34	39		T35	14
bins_for_gpio_bits[9]	auto[1]	auto[1]	2882716	1			T33	134		T34	196		T35	434
bins_for_gpio_bits[10]	auto[0]	auto[0]	2886438	1			T33	430		T34	533		T35	122
bins_for_gpio_bits[10]	auto[0]	auto[1]	84081	1			T33	31		T34	52		T35	11
bins_for_gpio_bits[10]	auto[1]	auto[0]	84285	1			T33	31		T34	52		T35	11
bins_for_gpio_bits[10]	auto[1]	auto[1]	2887677	1			T33	130		T34	245		T35	432
bins_for_gpio_bits[11]	auto[0]	auto[0]	2888872	1			T33	403		T34	570		T35	107
bins_for_gpio_bits[11]	auto[0]	auto[1]	83934	1			T33	37		T34	45		T35	12
bins_for_gpio_bits[11]	auto[1]	auto[0]	84143	1			T33	37		T34	45		T35	12
bins_for_gpio_bits[11]	auto[1]	auto[1]	2885532	1			T33	145		T34	222		T35	445
bins_for_gpio_bits[12]	auto[0]	auto[0]	2884245	1			T33	404		T34	536		T35	138
bins_for_gpio_bits[12]	auto[0]	auto[1]	83738	1			T33	33		T34	43		T35	11
bins_for_gpio_bits[12]	auto[1]	auto[0]	83895	1			T33	33		T34	43		T35	11
bins_for_gpio_bits[12]	auto[1]	auto[1]	2890603	1			T33	152		T34	260		T35	416
bins_for_gpio_bits[13]	auto[0]	auto[0]	2884498	1			T33	463		T34	589		T35	75
bins_for_gpio_bits[13]	auto[0]	auto[1]	83773	1			T33	32		T34	40		T35	9
bins_for_gpio_bits[13]	auto[1]	auto[0]	83932	1			T33	32		T34	41		T35	9
bins_for_gpio_bits[13]	auto[1]	auto[1]	2890278	1			T33	95		T34	212		T35	483
bins_for_gpio_bits[14]	auto[0]	auto[0]	2877289	1			T33	390		T34	565		T35	106
bins_for_gpio_bits[14]	auto[0]	auto[1]	83998	1			T33	33		T34	42		T35	12
bins_for_gpio_bits[14]	auto[1]	auto[0]	84207	1			T33	33		T34	42		T35	12
bins_for_gpio_bits[14]	auto[1]	auto[1]	2896987	1			T33	166		T34	233		T35	446
bins_for_gpio_bits[15]	auto[0]	auto[0]	2896696	1			T33	391		T34	631		T35	145
bins_for_gpio_bits[15]	auto[0]	auto[1]	84043	1			T33	36		T34	39		T35	17
bins_for_gpio_bits[15]	auto[1]	auto[0]	84204	1			T33	36		T34	40		T35	16
bins_for_gpio_bits[15]	auto[1]	auto[1]	2877538	1			T33	159		T34	172		T35	398
bins_for_gpio_bits[16]	auto[0]	auto[0]	2889202	1			T33	386		T34	606		T35	97
bins_for_gpio_bits[16]	auto[0]	auto[1]	83842	1			T33	35		T34	41		T35	10
bins_for_gpio_bits[16]	auto[1]	auto[0]	84010	1			T33	35		T34	42		T35	10
bins_for_gpio_bits[16]	auto[1]	auto[1]	2885427	1			T33	166		T34	193		T35	459
bins_for_gpio_bits[17]	auto[0]	auto[0]	2883824	1			T33	419		T34	597		T35	119
bins_for_gpio_bits[17]	auto[0]	auto[1]	83549	1			T33	34		T34	42		T35	12
bins_for_gpio_bits[17]	auto[1]	auto[0]	83747	1			T33	34		T34	43		T35	11
bins_for_gpio_bits[17]	auto[1]	auto[1]	2891361	1			T33	135		T34	200		T35	434
bins_for_gpio_bits[18]	auto[0]	auto[0]	2873480	1			T33	444		T34	582		T35	112
bins_for_gpio_bits[18]	auto[0]	auto[1]	83924	1			T33	30		T34	39		T35	8
bins_for_gpio_bits[18]	auto[1]	auto[0]	84140	1			T33	30		T34	39		T35	8
bins_for_gpio_bits[18]	auto[1]	auto[1]	2900937	1			T33	118		T34	222		T35	448
bins_for_gpio_bits[19]	auto[0]	auto[0]	2889717	1			T33	415		T34	574		T35	146
bins_for_gpio_bits[19]	auto[0]	auto[1]	83789	1			T33	35		T34	46		T35	21
bins_for_gpio_bits[19]	auto[1]	auto[0]	83962	1			T33	35		T34	47		T35	21
bins_for_gpio_bits[19]	auto[1]	auto[1]	2885013	1			T33	137		T34	215		T35	388
bins_for_gpio_bits[20]	auto[0]	auto[0]	2889536	1			T33	451		T34	563		T35	159
bins_for_gpio_bits[20]	auto[0]	auto[1]	83804	1			T33	29		T34	43		T35	17
bins_for_gpio_bits[20]	auto[1]	auto[0]	84010	1			T33	29		T34	43		T35	17
bins_for_gpio_bits[20]	auto[1]	auto[1]	2885131	1			T33	113		T34	233		T35	383
bins_for_gpio_bits[21]	auto[0]	auto[0]	2888728	1			T33	392		T34	544		T35	114
bins_for_gpio_bits[21]	auto[0]	auto[1]	83951	1			T33	37		T34	45		T35	13
bins_for_gpio_bits[21]	auto[1]	auto[0]	84146	1			T33	38		T34	45		T35	13
bins_for_gpio_bits[21]	auto[1]	auto[1]	2885656	1			T33	155		T34	248		T35	436
bins_for_gpio_bits[22]	auto[0]	auto[0]	2892640	1			T33	458		T34	552		T35	142
bins_for_gpio_bits[22]	auto[0]	auto[1]	84363	1			T33	28		T34	50		T35	17
bins_for_gpio_bits[22]	auto[1]	auto[0]	84531	1			T33	28		T34	51		T35	17
bins_for_gpio_bits[22]	auto[1]	auto[1]	2880947	1			T33	108		T34	229		T35	400
bins_for_gpio_bits[23]	auto[0]	auto[0]	2884369	1			T33	406		T34	610		T35	115
bins_for_gpio_bits[23]	auto[0]	auto[1]	84286	1			T33	39		T34	39		T35	14
bins_for_gpio_bits[23]	auto[1]	auto[0]	84448	1			T33	39		T34	40		T35	13
bins_for_gpio_bits[23]	auto[1]	auto[1]	2889378	1			T33	138		T34	193		T35	434
bins_for_gpio_bits[24]	auto[0]	auto[0]	2881067	1			T33	400		T34	592		T35	102
bins_for_gpio_bits[24]	auto[0]	auto[1]	83947	1			T33	31		T34	44		T35	13
bins_for_gpio_bits[24]	auto[1]	auto[0]	84177	1			T33	32		T34	45		T35	13
bins_for_gpio_bits[24]	auto[1]	auto[1]	2893290	1			T33	159		T34	201		T35	448
bins_for_gpio_bits[25]	auto[0]	auto[0]	2890601	1			T33	416		T34	611		T35	109
bins_for_gpio_bits[25]	auto[0]	auto[1]	83965	1			T33	34		T34	34		T35	13
bins_for_gpio_bits[25]	auto[1]	auto[0]	84189	1			T33	35		T34	35		T35	13
bins_for_gpio_bits[25]	auto[1]	auto[1]	2883726	1			T33	137		T34	202		T35	441
bins_for_gpio_bits[26]	auto[0]	auto[0]	2884790	1			T33	435		T34	555		T35	112
bins_for_gpio_bits[26]	auto[0]	auto[1]	83866	1			T33	34		T34	46		T35	11
bins_for_gpio_bits[26]	auto[1]	auto[0]	84012	1			T33	34		T34	46		T35	10
bins_for_gpio_bits[26]	auto[1]	auto[1]	2889813	1			T33	119		T34	235		T35	443
bins_for_gpio_bits[27]	auto[0]	auto[0]	2881797	1			T33	442		T34	582		T35	105
bins_for_gpio_bits[27]	auto[0]	auto[1]	83724	1			T33	32		T34	44		T35	12
bins_for_gpio_bits[27]	auto[1]	auto[0]	83898	1			T33	32		T34	44		T35	12
bins_for_gpio_bits[27]	auto[1]	auto[1]	2893062	1			T33	116		T34	212		T35	447
bins_for_gpio_bits[28]	auto[0]	auto[0]	2883434	1			T33	463		T34	597		T35	135
bins_for_gpio_bits[28]	auto[0]	auto[1]	84144	1			T33	29		T34	44		T35	16
bins_for_gpio_bits[28]	auto[1]	auto[0]	84341	1			T33	29		T34	44		T35	16
bins_for_gpio_bits[28]	auto[1]	auto[1]	2890562	1			T33	101		T34	197		T35	409
bins_for_gpio_bits[29]	auto[0]	auto[0]	2882031	1			T33	428		T34	536		T35	125
bins_for_gpio_bits[29]	auto[0]	auto[1]	83973	1			T33	36		T34	52		T35	14
bins_for_gpio_bits[29]	auto[1]	auto[0]	84128	1			T33	36		T34	53		T35	14
bins_for_gpio_bits[29]	auto[1]	auto[1]	2892349	1			T33	122		T34	241		T35	423
bins_for_gpio_bits[30]	auto[0]	auto[0]	2882111	1			T33	420		T34	565		T35	137
bins_for_gpio_bits[30]	auto[0]	auto[1]	83801	1			T33	32		T34	48		T35	16
bins_for_gpio_bits[30]	auto[1]	auto[0]	83999	1			T33	32		T34	48		T35	16
bins_for_gpio_bits[30]	auto[1]	auto[1]	2892570	1			T33	138		T34	221		T35	407
bins_for_gpio_bits[31]	auto[0]	auto[0]	2886679	1			T33	420		T34	542		T35	119
bins_for_gpio_bits[31]	auto[0]	auto[1]	83704	1			T33	32		T34	49		T35	11
bins_for_gpio_bits[31]	auto[1]	auto[0]	83914	1			T33	32		T34	50		T35	11
bins_for_gpio_bits[31]	auto[1]	auto[1]	2888184	1			T33	138		T34	241		T35	435