Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4123611 |
1 |
|
|
T33 |
340 |
|
T34 |
526 |
|
T35 |
292 |
| auto[1] |
1860117 |
1 |
|
|
T38 |
118 |
|
T40 |
1072 |
|
T41 |
249 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5747809 |
1 |
|
|
T33 |
340 |
|
T34 |
526 |
|
T35 |
292 |
| auto[1] |
235919 |
1 |
|
|
T38 |
6 |
|
T40 |
171 |
|
T41 |
13 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4136852 |
1 |
|
|
T33 |
340 |
|
T34 |
526 |
|
T35 |
292 |
| auto[1] |
1846876 |
1 |
|
|
T38 |
88 |
|
T40 |
864 |
|
T41 |
191 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
805745 |
1 |
|
|
T38 |
31 |
|
T40 |
337 |
|
T41 |
115 |
| auto[1] |
auto[0] |
auto[1] |
118080 |
1 |
|
|
T38 |
2 |
|
T40 |
85 |
|
T41 |
8 |
| auto[1] |
auto[1] |
auto[0] |
805212 |
1 |
|
|
T38 |
51 |
|
T40 |
356 |
|
T41 |
63 |
| auto[1] |
auto[1] |
auto[1] |
117839 |
1 |
|
|
T38 |
4 |
|
T40 |
86 |
|
T41 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |