Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4120886 |
1 |
|
|
T33 |
340 |
|
T34 |
526 |
|
T35 |
292 |
| auto[1] |
1862842 |
1 |
|
|
T38 |
99 |
|
T40 |
1199 |
|
T41 |
168 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5748928 |
1 |
|
|
T33 |
340 |
|
T34 |
526 |
|
T35 |
292 |
| auto[1] |
234800 |
1 |
|
|
T38 |
3 |
|
T40 |
249 |
|
T41 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4149551 |
1 |
|
|
T33 |
340 |
|
T34 |
526 |
|
T35 |
292 |
| auto[1] |
1834177 |
1 |
|
|
T38 |
53 |
|
T40 |
1232 |
|
T41 |
195 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
795701 |
1 |
|
|
T38 |
33 |
|
T40 |
432 |
|
T41 |
125 |
| auto[1] |
auto[0] |
auto[1] |
116568 |
1 |
|
|
T38 |
1 |
|
T40 |
112 |
|
T41 |
1 |
| auto[1] |
auto[1] |
auto[0] |
803676 |
1 |
|
|
T38 |
17 |
|
T40 |
551 |
|
T41 |
68 |
| auto[1] |
auto[1] |
auto[1] |
118232 |
1 |
|
|
T38 |
2 |
|
T40 |
137 |
|
T41 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |