Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4136408 |
1 |
|
|
T33 |
340 |
|
T34 |
526 |
|
T35 |
292 |
| auto[1] |
1847320 |
1 |
|
|
T38 |
107 |
|
T40 |
1297 |
|
T41 |
244 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5063947 |
1 |
|
|
T33 |
340 |
|
T34 |
526 |
|
T35 |
292 |
| auto[1] |
919781 |
1 |
|
|
T38 |
52 |
|
T40 |
605 |
|
T41 |
144 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4146816 |
1 |
|
|
T33 |
340 |
|
T34 |
526 |
|
T35 |
292 |
| auto[1] |
1836912 |
1 |
|
|
T38 |
96 |
|
T40 |
1231 |
|
T41 |
193 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
459195 |
1 |
|
|
T38 |
17 |
|
T40 |
269 |
|
T41 |
22 |
| auto[1] |
auto[0] |
auto[1] |
463344 |
1 |
|
|
T38 |
33 |
|
T40 |
250 |
|
T41 |
24 |
| auto[1] |
auto[1] |
auto[0] |
457936 |
1 |
|
|
T38 |
27 |
|
T40 |
357 |
|
T41 |
27 |
| auto[1] |
auto[1] |
auto[1] |
456437 |
1 |
|
|
T38 |
19 |
|
T40 |
355 |
|
T41 |
120 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |