Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4133312 |
1 |
|
|
T33 |
340 |
|
T34 |
526 |
|
T35 |
292 |
| auto[1] |
1850416 |
1 |
|
|
T38 |
76 |
|
T40 |
1383 |
|
T41 |
282 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5745898 |
1 |
|
|
T33 |
340 |
|
T34 |
526 |
|
T35 |
292 |
| auto[1] |
237830 |
1 |
|
|
T38 |
12 |
|
T40 |
221 |
|
T41 |
9 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4134412 |
1 |
|
|
T33 |
340 |
|
T34 |
526 |
|
T35 |
292 |
| auto[1] |
1849316 |
1 |
|
|
T38 |
113 |
|
T40 |
1119 |
|
T41 |
250 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
809990 |
1 |
|
|
T38 |
67 |
|
T40 |
270 |
|
T41 |
103 |
| auto[1] |
auto[0] |
auto[1] |
119575 |
1 |
|
|
T38 |
8 |
|
T40 |
70 |
|
T41 |
1 |
| auto[1] |
auto[1] |
auto[0] |
801496 |
1 |
|
|
T38 |
34 |
|
T40 |
628 |
|
T41 |
138 |
| auto[1] |
auto[1] |
auto[1] |
118255 |
1 |
|
|
T38 |
4 |
|
T40 |
151 |
|
T41 |
8 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |