Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4127262 |
1 |
|
|
T33 |
340 |
|
T34 |
526 |
|
T35 |
292 |
| auto[1] |
1856466 |
1 |
|
|
T38 |
120 |
|
T40 |
1269 |
|
T41 |
233 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5744644 |
1 |
|
|
T33 |
340 |
|
T34 |
526 |
|
T35 |
292 |
| auto[1] |
239084 |
1 |
|
|
T38 |
14 |
|
T40 |
212 |
|
T41 |
8 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4122611 |
1 |
|
|
T33 |
340 |
|
T34 |
526 |
|
T35 |
292 |
| auto[1] |
1861117 |
1 |
|
|
T38 |
107 |
|
T40 |
1065 |
|
T41 |
233 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
811959 |
1 |
|
|
T38 |
23 |
|
T40 |
330 |
|
T41 |
102 |
| auto[1] |
auto[0] |
auto[1] |
119853 |
1 |
|
|
T38 |
5 |
|
T40 |
88 |
|
T41 |
1 |
| auto[1] |
auto[1] |
auto[0] |
810074 |
1 |
|
|
T38 |
70 |
|
T40 |
523 |
|
T41 |
123 |
| auto[1] |
auto[1] |
auto[1] |
119231 |
1 |
|
|
T38 |
9 |
|
T40 |
124 |
|
T41 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |