Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	1529545	1			T25	1		T26	1		T27	1
all_pins[1]	1529545	1			T25	1		T26	1		T27	1
all_pins[2]	1529545	1			T25	1		T26	1		T27	1
all_pins[3]	1529545	1			T25	1		T26	1		T27	1
all_pins[4]	1529545	1			T25	1		T26	1		T27	1
all_pins[5]	1529545	1			T25	1		T26	1		T27	1
all_pins[6]	1529545	1			T25	1		T26	1		T27	1
all_pins[7]	1529545	1			T25	1		T26	1		T27	1
all_pins[8]	1529545	1			T25	1		T26	1		T27	1
all_pins[9]	1529545	1			T25	1		T26	1		T27	1
all_pins[10]	1529545	1			T25	1		T26	1		T27	1
all_pins[11]	1529545	1			T25	1		T26	1		T27	1
all_pins[12]	1529545	1			T25	1		T26	1		T27	1
all_pins[13]	1529545	1			T25	1		T26	1		T27	1
all_pins[14]	1529545	1			T25	1		T26	1		T27	1
all_pins[15]	1529545	1			T25	1		T26	1		T27	1
all_pins[16]	1529545	1			T25	1		T26	1		T27	1
all_pins[17]	1529545	1			T25	1		T26	1		T27	1
all_pins[18]	1529545	1			T25	1		T26	1		T27	1
all_pins[19]	1529545	1			T25	1		T26	1		T27	1
all_pins[20]	1529545	1			T25	1		T26	1		T27	1
all_pins[21]	1529545	1			T25	1		T26	1		T27	1
all_pins[22]	1529545	1			T25	1		T26	1		T27	1
all_pins[23]	1529545	1			T25	1		T26	1		T27	1
all_pins[24]	1529545	1			T25	1		T26	1		T27	1
all_pins[25]	1529545	1			T25	1		T26	1		T27	1
all_pins[26]	1529545	1			T25	1		T26	1		T27	1
all_pins[27]	1529545	1			T25	1		T26	1		T27	1
all_pins[28]	1529545	1			T25	1		T26	1		T27	1
all_pins[29]	1529545	1			T25	1		T26	1		T27	1
all_pins[30]	1529545	1			T25	1		T26	1		T27	1
all_pins[31]	1529545	1			T25	1		T26	1		T27	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	30460167	1			T25	32		T26	32		T27	32
values[0x1]	18485273	1			T30	1768		T31	7107		T32	342
transitions[0x0=>0x1]	11077947	1			T30	953		T31	4497		T32	208
transitions[0x1=>0x0]	11077800	1			T30	953		T31	4497		T32	208

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	950674	1			T25	1		T26	1		T27	1
all_pins[0]	values[0x1]	578871	1			T30	74		T31	183		T32	15
all_pins[0]	transitions[0x0=>0x1]	356705	1			T30	58		T31	133		T32	12
all_pins[0]	transitions[0x1=>0x0]	358747	1			T30	30		T31	150		T32	1
all_pins[1]	values[0x0]	950140	1			T25	1		T26	1		T27	1
all_pins[1]	values[0x1]	579405	1			T30	41		T31	279		T32	7
all_pins[1]	transitions[0x0=>0x1]	346489	1			T30	22		T31	231		T32	3
all_pins[1]	transitions[0x1=>0x0]	345955	1			T30	55		T31	135		T32	11
all_pins[2]	values[0x0]	951223	1			T25	1		T26	1		T27	1
all_pins[2]	values[0x1]	578322	1			T30	69		T31	135		T32	2
all_pins[2]	transitions[0x0=>0x1]	345243	1			T30	47		T31	69		T32	2
all_pins[2]	transitions[0x1=>0x0]	346326	1			T30	19		T31	213		T32	7
all_pins[3]	values[0x0]	951286	1			T25	1		T26	1		T27	1
all_pins[3]	values[0x1]	578259	1			T30	63		T31	184		T32	11
all_pins[3]	transitions[0x0=>0x1]	346827	1			T30	31		T31	150		T32	11
all_pins[3]	transitions[0x1=>0x0]	346890	1			T30	37		T31	101		T32	2
all_pins[4]	values[0x0]	952283	1			T25	1		T26	1		T27	1
all_pins[4]	values[0x1]	577262	1			T30	43		T31	198		T32	7
all_pins[4]	transitions[0x0=>0x1]	345711	1			T30	9		T31	111		T32	6
all_pins[4]	transitions[0x1=>0x0]	346708	1			T30	29		T31	97		T32	10
all_pins[5]	values[0x0]	952547	1			T25	1		T26	1		T27	1
all_pins[5]	values[0x1]	576998	1			T30	71		T31	330		T32	13
all_pins[5]	transitions[0x0=>0x1]	345538	1			T30	39		T31	242		T32	8
all_pins[5]	transitions[0x1=>0x0]	345802	1			T30	11		T31	110		T32	2
all_pins[6]	values[0x0]	948052	1			T25	1		T26	1		T27	1
all_pins[6]	values[0x1]	581493	1			T30	94		T31	232		T32	9
all_pins[6]	transitions[0x0=>0x1]	347668	1			T30	47		T31	105		T32	1
all_pins[6]	transitions[0x1=>0x0]	343173	1			T30	24		T31	203		T32	5
all_pins[7]	values[0x0]	953023	1			T25	1		T26	1		T27	1
all_pins[7]	values[0x1]	576522	1			T30	26		T31	255		T32	6
all_pins[7]	transitions[0x0=>0x1]	342488	1			T30	13		T31	123		T32	2
all_pins[7]	transitions[0x1=>0x0]	347459	1			T30	81		T31	100		T32	5
all_pins[8]	values[0x0]	951227	1			T25	1		T26	1		T27	1
all_pins[8]	values[0x1]	578318	1			T30	62		T31	261		T32	9
all_pins[8]	transitions[0x0=>0x1]	346070	1			T30	45		T31	167		T32	7
all_pins[8]	transitions[0x1=>0x0]	344274	1			T30	9		T31	161		T32	4
all_pins[9]	values[0x0]	954024	1			T25	1		T26	1		T27	1
all_pins[9]	values[0x1]	575521	1			T30	61		T31	211		T32	15
all_pins[9]	transitions[0x0=>0x1]	343375	1			T30	29		T31	153		T32	12
all_pins[9]	transitions[0x1=>0x0]	346172	1			T30	30		T31	203		T32	6
all_pins[10]	values[0x0]	953321	1			T25	1		T26	1		T27	1
all_pins[10]	values[0x1]	576224	1			T30	65		T31	317		T32	10
all_pins[10]	transitions[0x0=>0x1]	344596	1			T30	25		T31	233		T32	2
all_pins[10]	transitions[0x1=>0x0]	343893	1			T30	21		T31	127		T32	7
all_pins[11]	values[0x0]	952332	1			T25	1		T26	1		T27	1
all_pins[11]	values[0x1]	577213	1			T30	40		T31	211		T32	29
all_pins[11]	transitions[0x0=>0x1]	345417	1			T30	23		T31	73		T32	20
all_pins[11]	transitions[0x1=>0x0]	344428	1			T30	48		T31	179		T32	1
all_pins[12]	values[0x0]	953208	1			T25	1		T26	1		T27	1
all_pins[12]	values[0x1]	576337	1			T30	87		T31	193		T32	10
all_pins[12]	transitions[0x0=>0x1]	345125	1			T30	63		T31	94		T32	1
all_pins[12]	transitions[0x1=>0x0]	346001	1			T30	16		T31	112		T32	20
all_pins[13]	values[0x0]	948391	1			T25	1		T26	1		T27	1
all_pins[13]	values[0x1]	581154	1			T30	42		T31	161		T32	9
all_pins[13]	transitions[0x0=>0x1]	348537	1			T30	19		T31	120		T32	7
all_pins[13]	transitions[0x1=>0x0]	343720	1			T30	64		T31	152		T32	8
all_pins[14]	values[0x0]	947379	1			T25	1		T26	1		T27	1
all_pins[14]	values[0x1]	582166	1			T30	68		T31	253		T32	16
all_pins[14]	transitions[0x0=>0x1]	347274	1			T30	43		T31	160		T32	7
all_pins[14]	transitions[0x1=>0x0]	346262	1			T30	17		T31	68		T34	8
all_pins[15]	values[0x0]	950546	1			T25	1		T26	1		T27	1
all_pins[15]	values[0x1]	578999	1			T30	57		T31	147		T32	6
all_pins[15]	transitions[0x0=>0x1]	343456	1			T30	25		T31	73		T32	3
all_pins[15]	transitions[0x1=>0x0]	346623	1			T30	36		T31	179		T32	13
all_pins[16]	values[0x0]	951727	1			T25	1		T26	1		T27	1
all_pins[16]	values[0x1]	577818	1			T30	30		T31	264		T32	6
all_pins[16]	transitions[0x0=>0x1]	345956	1			T30	11		T31	173		T32	5
all_pins[16]	transitions[0x1=>0x0]	347137	1			T30	38		T31	56		T32	5
all_pins[17]	values[0x0]	954361	1			T25	1		T26	1		T27	1
all_pins[17]	values[0x1]	575184	1			T30	32		T31	282		T32	9
all_pins[17]	transitions[0x0=>0x1]	345219	1			T30	17		T31	147		T32	6
all_pins[17]	transitions[0x1=>0x0]	347853	1			T30	15		T31	129		T32	3
all_pins[18]	values[0x0]	951065	1			T25	1		T26	1		T27	1
all_pins[18]	values[0x1]	578480	1			T30	31		T31	226		T32	9
all_pins[18]	transitions[0x0=>0x1]	348901	1			T30	19		T31	119		T32	4
all_pins[18]	transitions[0x1=>0x0]	345605	1			T30	20		T31	175		T32	4
all_pins[19]	values[0x0]	951677	1			T25	1		T26	1		T27	1
all_pins[19]	values[0x1]	577868	1			T30	43		T31	224		T32	12
all_pins[19]	transitions[0x0=>0x1]	345534	1			T30	18		T31	130		T32	5
all_pins[19]	transitions[0x1=>0x0]	346146	1			T30	6		T31	132		T32	2
all_pins[20]	values[0x0]	951190	1			T25	1		T26	1		T27	1
all_pins[20]	values[0x1]	578355	1			T30	44		T31	228		T32	16
all_pins[20]	transitions[0x0=>0x1]	346750	1			T30	29		T31	126		T32	8
all_pins[20]	transitions[0x1=>0x0]	346263	1			T30	28		T31	122		T32	4
all_pins[21]	values[0x0]	952775	1			T25	1		T26	1		T27	1
all_pins[21]	values[0x1]	576770	1			T30	44		T31	171		T32	14
all_pins[21]	transitions[0x0=>0x1]	346817	1			T30	21		T31	112		T32	7
all_pins[21]	transitions[0x1=>0x0]	348402	1			T30	21		T31	169		T32	9
all_pins[22]	values[0x0]	952388	1			T25	1		T26	1		T27	1
all_pins[22]	values[0x1]	577157	1			T30	39		T31	235		T32	9
all_pins[22]	transitions[0x0=>0x1]	344320	1			T30	23		T31	197		T32	6
all_pins[22]	transitions[0x1=>0x0]	343933	1			T30	28		T31	133		T32	11
all_pins[23]	values[0x0]	954132	1			T25	1		T26	1		T27	1
all_pins[23]	values[0x1]	575413	1			T30	33		T31	199		T32	11
all_pins[23]	transitions[0x0=>0x1]	344891	1			T30	19		T31	103		T32	5
all_pins[23]	transitions[0x1=>0x0]	346635	1			T30	25		T31	139		T32	3
all_pins[24]	values[0x0]	953887	1			T25	1		T26	1		T27	1
all_pins[24]	values[0x1]	575658	1			T30	68		T31	232		T32	9
all_pins[24]	transitions[0x0=>0x1]	345555	1			T30	57		T31	168		T32	5
all_pins[24]	transitions[0x1=>0x0]	345310	1			T30	22		T31	135		T32	7
all_pins[25]	values[0x0]	953454	1			T25	1		T26	1		T27	1
all_pins[25]	values[0x1]	576091	1			T30	75		T31	280		T32	21
all_pins[25]	transitions[0x0=>0x1]	346587	1			T30	35		T31	196		T32	17
all_pins[25]	transitions[0x1=>0x0]	346154	1			T30	28		T31	148		T32	5
all_pins[26]	values[0x0]	951886	1			T25	1		T26	1		T27	1
all_pins[26]	values[0x1]	577659	1			T30	74		T31	168		T32	3
all_pins[26]	transitions[0x0=>0x1]	346910	1			T30	28		T31	66		T34	10
all_pins[26]	transitions[0x1=>0x0]	345342	1			T30	29		T31	178		T32	18
all_pins[27]	values[0x0]	952930	1			T25	1		T26	1		T27	1
all_pins[27]	values[0x1]	576615	1			T30	63		T31	257		T32	12
all_pins[27]	transitions[0x0=>0x1]	344695	1			T30	19		T31	181		T32	10
all_pins[27]	transitions[0x1=>0x0]	345739	1			T30	30		T31	92		T32	1
all_pins[28]	values[0x0]	952544	1			T25	1		T26	1		T27	1
all_pins[28]	values[0x1]	577001	1			T30	34		T31	192		T32	10
all_pins[28]	transitions[0x0=>0x1]	346249	1			T30	8		T31	131		T32	6
all_pins[28]	transitions[0x1=>0x0]	345863	1			T30	37		T31	196		T32	8
all_pins[29]	values[0x0]	952554	1			T25	1		T26	1		T27	1
all_pins[29]	values[0x1]	576991	1			T30	84		T31	161		T32	14
all_pins[29]	transitions[0x0=>0x1]	345935	1			T30	56		T31	126		T32	14
all_pins[29]	transitions[0x1=>0x0]	345945	1			T30	6		T31	157		T32	10
all_pins[30]	values[0x0]	955456	1			T25	1		T26	1		T27	1
all_pins[30]	values[0x1]	574089	1			T30	65		T31	238		T32	9
all_pins[30]	transitions[0x0=>0x1]	343252	1			T30	29		T31	175		T32	2
all_pins[30]	transitions[0x1=>0x0]	346154	1			T30	48		T31	98		T32	7
all_pins[31]	values[0x0]	948485	1			T25	1		T26	1		T27	1
all_pins[31]	values[0x1]	581060	1			T30	46		T31	200		T32	4
all_pins[31]	transitions[0x0=>0x1]	349857	1			T30	26		T31	110		T32	4
all_pins[31]	transitions[0x1=>0x0]	342886	1			T30	45		T31	148		T32	9