Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	6383451	1			T25	332		T26	144		T27	334
all_values[1]	6383451	1			T25	332		T26	144		T27	334
all_values[2]	6383451	1			T25	332		T26	144		T27	334
all_values[3]	6383451	1			T25	332		T26	144		T27	334
all_values[4]	6383451	1			T25	332		T26	144		T27	334
all_values[5]	6383451	1			T25	332		T26	144		T27	334
all_values[6]	6383451	1			T25	332		T26	144		T27	334
all_values[7]	6383451	1			T25	332		T26	144		T27	334
all_values[8]	6383451	1			T25	332		T26	144		T27	334
all_values[9]	6383451	1			T25	332		T26	144		T27	334
all_values[10]	6383451	1			T25	332		T26	144		T27	334
all_values[11]	6383451	1			T25	332		T26	144		T27	334
all_values[12]	6383451	1			T25	332		T26	144		T27	334
all_values[13]	6383451	1			T25	332		T26	144		T27	334
all_values[14]	6383451	1			T25	332		T26	144		T27	334
all_values[15]	6383451	1			T25	332		T26	144		T27	334
all_values[16]	6383451	1			T25	332		T26	144		T27	334
all_values[17]	6383451	1			T25	332		T26	144		T27	334
all_values[18]	6383451	1			T25	332		T26	144		T27	334
all_values[19]	6383451	1			T25	332		T26	144		T27	334
all_values[20]	6383451	1			T25	332		T26	144		T27	334
all_values[21]	6383451	1			T25	332		T26	144		T27	334
all_values[22]	6383451	1			T25	332		T26	144		T27	334
all_values[23]	6383451	1			T25	332		T26	144		T27	334
all_values[24]	6383451	1			T25	332		T26	144		T27	334
all_values[25]	6383451	1			T25	332		T26	144		T27	334
all_values[26]	6383451	1			T25	332		T26	144		T27	334
all_values[27]	6383451	1			T25	332		T26	144		T27	334
all_values[28]	6383451	1			T25	332		T26	144		T27	334
all_values[29]	6383451	1			T25	332		T26	144		T27	334
all_values[30]	6383451	1			T25	332		T26	144		T27	334
all_values[31]	6383451	1			T25	332		T26	144		T27	334

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

138076686

1

T25

10624

T26

4608

T27

10688

auto[1]

66193746

1

T30

4117

T31

22237

T32

991

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

84784298

1

T25

10624

T26

4608

T27

10688

auto[1]

119486134

1

T30

6779

T31

42239

T32

1275

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

202359702

1

T25

10624

T26

4608

T27

10688

auto[1]

1910730

1

T32

131

T1

878

T19

203

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	2440800	1			T25	332		T26	144		T27	334
all_values[0]	auto[0]	auto[0]	auto[1]	1838073	1			T30	84		T31	678		T32	16
all_values[0]	auto[0]	auto[1]	auto[0]	213558	1			T30	10		T31	82		T32	15
all_values[0]	auto[0]	auto[1]	auto[1]	1831371	1			T30	138		T31	524		T32	26
all_values[0]	auto[1]	auto[0]	auto[1]	30317	1			T32	3		T1	16		T19	3
all_values[0]	auto[1]	auto[1]	auto[1]	29332	1			T32	1		T1	10		T19	2
all_values[1]	auto[0]	auto[0]	auto[0]	2438318	1			T25	332		T26	144		T27	334
all_values[1]	auto[0]	auto[0]	auto[1]	1849123	1			T30	131		T31	543		T32	19
all_values[1]	auto[0]	auto[1]	auto[0]	212393	1			T30	13		T31	20		T32	15
all_values[1]	auto[0]	auto[1]	auto[1]	1824194	1			T30	88		T31	845		T32	15
all_values[1]	auto[1]	auto[0]	auto[1]	30018	1			T32	5		T1	12		T19	4
all_values[1]	auto[1]	auto[1]	auto[1]	29405	1			T32	1		T1	21		T19	3
all_values[2]	auto[0]	auto[0]	auto[0]	2440375	1			T25	332		T26	144		T27	334
all_values[2]	auto[0]	auto[0]	auto[1]	1848208	1			T30	105		T31	972		T32	23
all_values[2]	auto[0]	auto[1]	auto[0]	209839	1			T30	12		T31	51		T32	11
all_values[2]	auto[0]	auto[1]	auto[1]	1825232	1			T30	123		T31	397		T32	5
all_values[2]	auto[1]	auto[0]	auto[1]	29589	1			T32	2		T1	15		T19	2
all_values[2]	auto[1]	auto[1]	auto[1]	30208	1			T1	13		T19	3		T100	49
all_values[3]	auto[0]	auto[0]	auto[0]	2438790	1			T25	332		T26	144		T27	334
all_values[3]	auto[0]	auto[0]	auto[1]	1837717	1			T30	93		T31	821		T32	25
all_values[3]	auto[0]	auto[1]	auto[0]	212103	1			T30	18		T31	90		T32	5
all_values[3]	auto[0]	auto[1]	auto[1]	1835077	1			T30	125		T31	462		T32	17
all_values[3]	auto[1]	auto[0]	auto[1]	30286	1			T32	2		T1	16		T19	3
all_values[3]	auto[1]	auto[1]	auto[1]	29478	1			T32	3		T1	14		T100	42
all_values[4]	auto[0]	auto[0]	auto[0]	2440123	1			T25	332		T26	144		T27	334
all_values[4]	auto[0]	auto[0]	auto[1]	1837655	1			T30	119		T31	788		T32	11
all_values[4]	auto[0]	auto[1]	auto[0]	208958	1			T30	20		T31	75		T32	12
all_values[4]	auto[0]	auto[1]	auto[1]	1837033	1			T30	85		T31	557		T32	14
all_values[4]	auto[1]	auto[0]	auto[1]	30037	1			T32	5		T1	16		T19	3
all_values[4]	auto[1]	auto[1]	auto[1]	29645	1			T1	8		T19	3		T100	38
all_values[5]	auto[0]	auto[0]	auto[0]	2439249	1			T25	332		T26	144		T27	334
all_values[5]	auto[0]	auto[0]	auto[1]	1858229	1			T30	72		T31	341		T32	27
all_values[5]	auto[0]	auto[1]	auto[0]	207805	1			T30	20		T31	110		T32	11
all_values[5]	auto[0]	auto[1]	auto[1]	1818361	1			T30	140		T31	978		T32	15
all_values[5]	auto[1]	auto[0]	auto[1]	30454	1			T32	4		T1	14		T19	6
all_values[5]	auto[1]	auto[1]	auto[1]	29353	1			T32	1		T1	16		T19	3
all_values[6]	auto[0]	auto[0]	auto[0]	2440660	1			T25	332		T26	144		T27	334
all_values[6]	auto[0]	auto[0]	auto[1]	1830535	1			T30	65		T31	686		T32	17
all_values[6]	auto[0]	auto[1]	auto[0]	212308	1			T30	17		T31	95		T32	24
all_values[6]	auto[0]	auto[1]	auto[1]	1840332	1			T30	166		T31	647		T32	10
all_values[6]	auto[1]	auto[0]	auto[1]	29951	1			T32	2		T1	18		T19	4
all_values[6]	auto[1]	auto[1]	auto[1]	29665	1			T32	2		T1	14		T19	2
all_values[7]	auto[0]	auto[0]	auto[0]	2440124	1			T25	332		T26	144		T27	334
all_values[7]	auto[0]	auto[0]	auto[1]	1853224	1			T30	147		T31	725		T32	20
all_values[7]	auto[0]	auto[1]	auto[0]	210963	1			T30	10		T31	48		T32	10
all_values[7]	auto[0]	auto[1]	auto[1]	1819491	1			T30	59		T31	611		T32	7
all_values[7]	auto[1]	auto[0]	auto[1]	30210	1			T32	5		T1	17		T19	6
all_values[7]	auto[1]	auto[1]	auto[1]	29439	1			T1	11		T19	2		T100	33
all_values[8]	auto[0]	auto[0]	auto[0]	2441283	1			T25	332		T26	144		T27	334
all_values[8]	auto[0]	auto[0]	auto[1]	1831397	1			T30	65		T31	536		T32	3
all_values[8]	auto[0]	auto[1]	auto[0]	213637	1			T30	23		T31	98		T32	23
all_values[8]	auto[0]	auto[1]	auto[1]	1837584	1			T30	131		T31	797		T32	17
all_values[8]	auto[1]	auto[0]	auto[1]	29754	1			T32	2		T1	14		T19	2
all_values[8]	auto[1]	auto[1]	auto[1]	29796	1			T1	16		T19	3		T100	30
all_values[9]	auto[0]	auto[0]	auto[0]	2441596	1			T25	332		T26	144		T27	334
all_values[9]	auto[0]	auto[0]	auto[1]	1843762	1			T30	103		T31	742		T32	23
all_values[9]	auto[0]	auto[1]	auto[0]	209981	1			T30	17		T31	42		T32	8
all_values[9]	auto[0]	auto[1]	auto[1]	1828224	1			T30	121		T31	615		T32	22
all_values[9]	auto[1]	auto[0]	auto[1]	30278	1			T32	4		T1	16		T19	7
all_values[9]	auto[1]	auto[1]	auto[1]	29610	1			T32	2		T1	10		T19	2
all_values[10]	auto[0]	auto[0]	auto[0]	2439507	1			T25	332		T26	144		T27	334
all_values[10]	auto[0]	auto[0]	auto[1]	1856953	1			T30	88		T31	402		T32	9
all_values[10]	auto[0]	auto[1]	auto[0]	209154	1			T30	28		T31	143		T32	29
all_values[10]	auto[0]	auto[1]	auto[1]	1818201	1			T30	122		T31	884		T32	16
all_values[10]	auto[1]	auto[0]	auto[1]	29912	1			T32	2		T1	17		T19	5
all_values[10]	auto[1]	auto[1]	auto[1]	29724	1			T32	2		T1	9		T19	4
all_values[11]	auto[0]	auto[0]	auto[0]	2436298	1			T25	332		T26	144		T27	334
all_values[11]	auto[0]	auto[0]	auto[1]	1844600	1			T30	111		T31	784		T32	15
all_values[11]	auto[0]	auto[1]	auto[0]	208431	1			T30	16		T31	27		T32	7
all_values[11]	auto[0]	auto[1]	auto[1]	1834378	1			T30	86		T31	578		T32	42
all_values[11]	auto[1]	auto[0]	auto[1]	29985	1			T32	3		T1	15		T19	3
all_values[11]	auto[1]	auto[1]	auto[1]	29759	1			T32	2		T1	19		T19	1
all_values[12]	auto[0]	auto[0]	auto[0]	2438662	1			T25	332		T26	144		T27	334
all_values[12]	auto[0]	auto[0]	auto[1]	1845518	1			T30	61		T31	675		T32	26
all_values[12]	auto[0]	auto[1]	auto[0]	208078	1			T30	23		T31	90		T32	15
all_values[12]	auto[0]	auto[1]	auto[1]	1831090	1			T30	163		T31	597		T32	10
all_values[12]	auto[1]	auto[0]	auto[1]	30192	1			T32	4		T1	11		T19	3
all_values[12]	auto[1]	auto[1]	auto[1]	29911	1			T32	2		T1	18		T19	2
all_values[13]	auto[0]	auto[0]	auto[0]	2434629	1			T25	332		T26	144		T27	334
all_values[13]	auto[0]	auto[0]	auto[1]	1839538	1			T30	85		T31	847		T32	16
all_values[13]	auto[0]	auto[1]	auto[0]	208939	1			T30	10		T31	51		T32	19
all_values[13]	auto[0]	auto[1]	auto[1]	1840320	1			T30	92		T31	447		T32	16
all_values[13]	auto[1]	auto[0]	auto[1]	30197	1			T32	4		T1	13		T19	7
all_values[13]	auto[1]	auto[1]	auto[1]	29828	1			T1	15		T19	1		T100	35
all_values[14]	auto[0]	auto[0]	auto[0]	2439766	1			T25	332		T26	144		T27	334
all_values[14]	auto[0]	auto[0]	auto[1]	1853159	1			T30	70		T31	601		T32	13
all_values[14]	auto[0]	auto[1]	auto[0]	209296	1			T30	29		T31	48		T32	11
all_values[14]	auto[0]	auto[1]	auto[1]	1821432	1			T30	142		T31	698		T32	23
all_values[14]	auto[1]	auto[0]	auto[1]	30004	1			T32	2		T1	12		T19	3
all_values[14]	auto[1]	auto[1]	auto[1]	29794	1			T32	2		T1	16		T19	3
all_values[15]	auto[0]	auto[0]	auto[0]	2438313	1			T25	332		T26	144		T27	334
all_values[15]	auto[0]	auto[0]	auto[1]	1857896	1			T30	109		T31	937		T32	35
all_values[15]	auto[0]	auto[1]	auto[0]	210084	1			T30	12		T31	22		T32	11
all_values[15]	auto[0]	auto[1]	auto[1]	1817753	1			T30	104		T31	411		T32	5
all_values[15]	auto[1]	auto[0]	auto[1]	30056	1			T32	6		T1	5		T19	6
all_values[15]	auto[1]	auto[1]	auto[1]	29349	1			T32	1		T1	17		T19	1
all_values[16]	auto[0]	auto[0]	auto[0]	2438232	1			T25	332		T26	144		T27	334
all_values[16]	auto[0]	auto[0]	auto[1]	1844933	1			T30	120		T31	568		T32	10
all_values[16]	auto[0]	auto[1]	auto[0]	209928	1			T30	30		T31	72		T32	11
all_values[16]	auto[0]	auto[1]	auto[1]	1830477	1			T30	76		T31	781		T32	11
all_values[16]	auto[1]	auto[0]	auto[1]	30037	1			T32	3		T1	13		T19	4
all_values[16]	auto[1]	auto[1]	auto[1]	29844	1			T1	17		T19	3		T100	42
all_values[17]	auto[0]	auto[0]	auto[0]	2441148	1			T25	332		T26	144		T27	334
all_values[17]	auto[0]	auto[0]	auto[1]	1853824	1			T30	120		T31	507		T32	35
all_values[17]	auto[0]	auto[1]	auto[0]	211990	1			T30	17		T31	72		T32	14
all_values[17]	auto[0]	auto[1]	auto[1]	1816918	1			T30	91		T31	789		T32	9
all_values[17]	auto[1]	auto[0]	auto[1]	30290	1			T32	2		T1	19		T19	4
all_values[17]	auto[1]	auto[1]	auto[1]	29281	1			T1	7		T100	40		T101	18
all_values[18]	auto[0]	auto[0]	auto[0]	2439345	1			T25	332		T26	144		T27	334
all_values[18]	auto[0]	auto[0]	auto[1]	1838771	1			T30	165		T31	751		T32	20
all_values[18]	auto[0]	auto[1]	auto[0]	210772	1			T30	1		T31	52		T32	18
all_values[18]	auto[0]	auto[1]	auto[1]	1834869	1			T30	62		T31	599		T32	10
all_values[18]	auto[1]	auto[0]	auto[1]	29926	1			T32	1		T1	18		T19	4
all_values[18]	auto[1]	auto[1]	auto[1]	29768	1			T32	2		T1	9		T19	1
all_values[19]	auto[0]	auto[0]	auto[0]	2440531	1			T25	332		T26	144		T27	334
all_values[19]	auto[0]	auto[0]	auto[1]	1840510	1			T30	143		T31	652		T32	17
all_values[19]	auto[0]	auto[1]	auto[0]	210479	1			T30	1		T31	32		T32	26
all_values[19]	auto[0]	auto[1]	auto[1]	1832301	1			T30	94		T31	702		T32	19
all_values[19]	auto[1]	auto[0]	auto[1]	30041	1			T32	2		T1	11		T19	3
all_values[19]	auto[1]	auto[1]	auto[1]	29589	1			T32	2		T1	14		T19	1
all_values[20]	auto[0]	auto[0]	auto[0]	2443346	1			T25	332		T26	144		T27	334
all_values[20]	auto[0]	auto[0]	auto[1]	1829997	1			T30	110		T31	595		T32	20
all_values[20]	auto[0]	auto[1]	auto[0]	211328	1			T30	34		T31	95		T32	9
all_values[20]	auto[0]	auto[1]	auto[1]	1839274	1			T30	90		T31	706		T32	30
all_values[20]	auto[1]	auto[0]	auto[1]	29872	1			T32	2		T1	8		T19	5
all_values[20]	auto[1]	auto[1]	auto[1]	29634	1			T32	1		T1	14		T19	2
all_values[21]	auto[0]	auto[0]	auto[0]	2441192	1			T25	332		T26	144		T27	334
all_values[21]	auto[0]	auto[0]	auto[1]	1858164	1			T30	119		T31	926		T32	29
all_values[21]	auto[0]	auto[1]	auto[0]	209882	1			T30	15		T31	28		T32	10
all_values[21]	auto[0]	auto[1]	auto[1]	1814416	1			T30	95		T31	420		T32	19
all_values[21]	auto[1]	auto[0]	auto[1]	30616	1			T32	2		T1	13		T19	4
all_values[21]	auto[1]	auto[1]	auto[1]	29181	1			T32	3		T1	12		T19	1
all_values[22]	auto[0]	auto[0]	auto[0]	2436431	1			T25	332		T26	144		T27	334
all_values[22]	auto[0]	auto[0]	auto[1]	1846407	1			T30	106		T31	620		T32	24
all_values[22]	auto[0]	auto[1]	auto[0]	207172	1			T30	26		T31	85		T32	9
all_values[22]	auto[0]	auto[1]	auto[1]	1834008	1			T30	97		T31	670		T32	12
all_values[22]	auto[1]	auto[0]	auto[1]	29855	1			T32	2		T1	15		T19	6
all_values[22]	auto[1]	auto[1]	auto[1]	29578	1			T32	1		T1	17		T19	2
all_values[23]	auto[0]	auto[0]	auto[0]	2440450	1			T25	332		T26	144		T27	334
all_values[23]	auto[0]	auto[0]	auto[1]	1843610	1			T30	154		T31	804		T32	34
all_values[23]	auto[0]	auto[1]	auto[0]	209840	1			T30	14		T31	20		T32	7
all_values[23]	auto[0]	auto[1]	auto[1]	1830013	1			T30	70		T31	506		T32	13
all_values[23]	auto[1]	auto[0]	auto[1]	29957	1			T32	3		T1	16		T19	2
all_values[23]	auto[1]	auto[1]	auto[1]	29581	1			T32	1		T1	12		T19	2
all_values[24]	auto[0]	auto[0]	auto[0]	2436883	1			T25	332		T26	144		T27	334
all_values[24]	auto[0]	auto[0]	auto[1]	1856634	1			T30	96		T31	559		T32	30
all_values[24]	auto[0]	auto[1]	auto[0]	210470	1			T30	15		T31	79		T32	16
all_values[24]	auto[0]	auto[1]	auto[1]	1819882	1			T30	121		T31	718		T32	10
all_values[24]	auto[1]	auto[0]	auto[1]	30425	1			T32	1		T1	5		T19	5
all_values[24]	auto[1]	auto[1]	auto[1]	29157	1			T32	2		T1	17		T19	3
all_values[25]	auto[0]	auto[0]	auto[0]	2436132	1			T25	332		T26	144		T27	334
all_values[25]	auto[0]	auto[0]	auto[1]	1851219	1			T30	83		T31	609		T32	11
all_values[25]	auto[0]	auto[1]	auto[0]	208946	1			T30	15		T31	53		T32	7
all_values[25]	auto[0]	auto[1]	auto[1]	1827367	1			T30	144		T31	734		T32	32
all_values[25]	auto[1]	auto[0]	auto[1]	30240	1			T32	1		T1	12		T19	4
all_values[25]	auto[1]	auto[1]	auto[1]	29547	1			T32	2		T1	12		T19	3
all_values[26]	auto[0]	auto[0]	auto[0]	2441952	1			T25	332		T26	144		T27	334
all_values[26]	auto[0]	auto[0]	auto[1]	1844376	1			T30	87		T31	839		T32	29
all_values[26]	auto[0]	auto[1]	auto[0]	211061	1			T30	9		T31	71		T32	21
all_values[26]	auto[0]	auto[1]	auto[1]	1826329	1			T30	144		T31	469		T32	6
all_values[26]	auto[1]	auto[0]	auto[1]	29979	1			T32	4		T1	13		T19	4
all_values[26]	auto[1]	auto[1]	auto[1]	29754	1			T32	1		T1	11		T19	2
all_values[27]	auto[0]	auto[0]	auto[0]	2440276	1			T25	332		T26	144		T27	334
all_values[27]	auto[0]	auto[0]	auto[1]	1848566	1			T30	84		T31	616		T32	17
all_values[27]	auto[0]	auto[1]	auto[0]	209039	1			T30	31		T31	117		T32	7
all_values[27]	auto[0]	auto[1]	auto[1]	1826052	1			T30	120		T31	688		T32	28
all_values[27]	auto[1]	auto[0]	auto[1]	29938	1			T32	3		T1	16		T19	3
all_values[27]	auto[1]	auto[1]	auto[1]	29580	1			T32	1		T1	8		T19	3
all_values[28]	auto[0]	auto[0]	auto[0]	2442814	1			T25	332		T26	144		T27	334
all_values[28]	auto[0]	auto[0]	auto[1]	1832727	1			T30	94		T31	812		T32	17
all_values[28]	auto[0]	auto[1]	auto[0]	208109	1			T30	20		T31	48		T32	15
all_values[28]	auto[0]	auto[1]	auto[1]	1839954	1			T30	73		T31	546		T32	14
all_values[28]	auto[1]	auto[0]	auto[1]	30214	1			T32	2		T1	18		T19	1
all_values[28]	auto[1]	auto[1]	auto[1]	29633	1			T32	3		T1	13		T19	3
all_values[29]	auto[0]	auto[0]	auto[0]	2439104	1			T25	332		T26	144		T27	334
all_values[29]	auto[0]	auto[0]	auto[1]	1840071	1			T30	66		T31	854		T32	5
all_values[29]	auto[0]	auto[1]	auto[0]	208789	1			T30	17		T31	47		T32	7
all_values[29]	auto[0]	auto[1]	auto[1]	1835550	1			T30	158		T31	454		T32	21
all_values[29]	auto[1]	auto[0]	auto[1]	30158	1			T32	1		T1	9		T19	4
all_values[29]	auto[1]	auto[1]	auto[1]	29779	1			T32	1		T1	20		T19	1
all_values[30]	auto[0]	auto[0]	auto[0]	2439567	1			T25	332		T26	144		T27	334
all_values[30]	auto[0]	auto[0]	auto[1]	1858793	1			T30	56		T31	673		T32	25
all_values[30]	auto[0]	auto[1]	auto[0]	210361	1			T30	36		T31	67		T32	13
all_values[30]	auto[0]	auto[1]	auto[1]	1814891	1			T30	131		T31	653		T32	14
all_values[30]	auto[1]	auto[0]	auto[1]	30302	1			T32	3		T1	15		T19	7
all_values[30]	auto[1]	auto[1]	auto[1]	29537	1			T32	2		T1	16		T19	3
all_values[31]	auto[0]	auto[0]	auto[0]	2434774	1			T25	332		T26	144		T27	334
all_values[31]	auto[0]	auto[0]	auto[1]	1838530	1			T30	124		T31	667		T32	11
all_values[31]	auto[0]	auto[1]	auto[0]	209935	1			T30	14		T31	98		T32	22
all_values[31]	auto[0]	auto[1]	auto[1]	1840311	1			T30	93		T31	626		T32	4
all_values[31]	auto[1]	auto[0]	auto[1]	30207	1			T32	3		T1	13		T19	9
all_values[31]	auto[1]	auto[1]	auto[1]	29694	1			T1	11		T19	2		T100	43

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal