Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	6359726	1			T25	604		T26	190		T27	641
bins_for_gpio_bits[1]	6359726	1			T25	604		T26	190		T27	641
bins_for_gpio_bits[2]	6359726	1			T25	604		T26	190		T27	641
bins_for_gpio_bits[3]	6359726	1			T25	604		T26	190		T27	641
bins_for_gpio_bits[4]	6359726	1			T25	604		T26	190		T27	641
bins_for_gpio_bits[5]	6359726	1			T25	604		T26	190		T27	641
bins_for_gpio_bits[6]	6359726	1			T25	604		T26	190		T27	641
bins_for_gpio_bits[7]	6359726	1			T25	604		T26	190		T27	641
bins_for_gpio_bits[8]	6359726	1			T25	604		T26	190		T27	641
bins_for_gpio_bits[9]	6359726	1			T25	604		T26	190		T27	641
bins_for_gpio_bits[10]	6359726	1			T25	604		T26	190		T27	641
bins_for_gpio_bits[11]	6359726	1			T25	604		T26	190		T27	641
bins_for_gpio_bits[12]	6359726	1			T25	604		T26	190		T27	641
bins_for_gpio_bits[13]	6359726	1			T25	604		T26	190		T27	641
bins_for_gpio_bits[14]	6359726	1			T25	604		T26	190		T27	641
bins_for_gpio_bits[15]	6359726	1			T25	604		T26	190		T27	641
bins_for_gpio_bits[16]	6359726	1			T25	604		T26	190		T27	641
bins_for_gpio_bits[17]	6359726	1			T25	604		T26	190		T27	641
bins_for_gpio_bits[18]	6359726	1			T25	604		T26	190		T27	641
bins_for_gpio_bits[19]	6359726	1			T25	604		T26	190		T27	641
bins_for_gpio_bits[20]	6359726	1			T25	604		T26	190		T27	641
bins_for_gpio_bits[21]	6359726	1			T25	604		T26	190		T27	641
bins_for_gpio_bits[22]	6359726	1			T25	604		T26	190		T27	641
bins_for_gpio_bits[23]	6359726	1			T25	604		T26	190		T27	641
bins_for_gpio_bits[24]	6359726	1			T25	604		T26	190		T27	641
bins_for_gpio_bits[25]	6359726	1			T25	604		T26	190		T27	641
bins_for_gpio_bits[26]	6359726	1			T25	604		T26	190		T27	641
bins_for_gpio_bits[27]	6359726	1			T25	604		T26	190		T27	641
bins_for_gpio_bits[28]	6359726	1			T25	604		T26	190		T27	641
bins_for_gpio_bits[29]	6359726	1			T25	604		T26	190		T27	641
bins_for_gpio_bits[30]	6359726	1			T25	604		T26	190		T27	641
bins_for_gpio_bits[31]	6359726	1			T25	604		T26	190		T27	641

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

104582636

1

T25

5219

T26

3863

T27

15710

auto[1]

98928596

1

T25

14109

T26

2217

T27

4802

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

169297033

1

T25

10795

T26

4609

T27

15342

auto[1]

34214199

1

T25

8533

T26

1471

T27

5170

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

159274554

1

T25

10755

T26

4675

T27

11092

auto[1]

44236678

1

T25

8573

T26

1405

T27

9420

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	2276342	1			T25	30		T26	72		T27	219
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	2163156	1			T25	196		T26	49		T27	53
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	538922	1			T25	114		T26	18		T27	61
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	466858	1			T26	33		T27	216		T29	271
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	381466	1			T25	114		T27	23		T29	33
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	532982	1			T25	150		T26	18		T27	69
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	2262399	1			T25	25		T26	71		T27	217
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	2178720	1			T25	186		T26	46		T27	47
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	539738	1			T25	118		T26	14		T27	87
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	465918	1			T26	41		T27	195		T29	190
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	381645	1			T25	148		T27	26		T29	18
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	531306	1			T25	127		T26	18		T27	69
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	2260110	1			T25	31		T26	59		T27	143
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	2175247	1			T25	154		T26	52		T27	30
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	537490	1			T25	167		T26	39		T27	92
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	470705	1			T26	14		T27	220		T29	220
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	383985	1			T25	118		T27	49		T29	25
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	532189	1			T25	134		T26	26		T27	107
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	2243720	1			T25	33		T26	78		T27	264
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	2197392	1			T25	154		T26	51		T27	56
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	538717	1			T25	158		T26	18		T27	82
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	466441	1			T26	17		T27	169		T29	273
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	382138	1			T25	132		T27	21		T29	32
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	531318	1			T25	127		T26	26		T27	49
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	2260792	1			T25	30		T26	76		T27	188
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	2175769	1			T25	225		T26	41		T27	44
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	538092	1			T25	133		T26	30		T27	107
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	467216	1			T26	13		T27	184		T29	271
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	381913	1			T25	116		T27	38		T29	34
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	535944	1			T25	100		T26	30		T27	80
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	2255070	1			T25	28		T26	71		T27	236
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	2184259	1			T25	181		T26	48		T27	44
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	534423	1			T25	119		T26	16		T27	94
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	469632	1			T26	35		T27	135		T29	343
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	382273	1			T25	142		T27	37		T29	27
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	534069	1			T25	134		T26	20		T27	95
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	2270967	1			T25	33		T26	74		T27	185
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	2171169	1			T25	144		T26	39		T27	52
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	539057	1			T25	120		T26	30		T27	109
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	463248	1			T26	13		T27	175		T29	337
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	383047	1			T25	158		T27	37		T29	29
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	532238	1			T25	149		T26	34		T27	83
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	2263846	1			T25	28		T26	62		T27	231
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	2176359	1			T25	158		T26	59		T27	36
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	537823	1			T25	134		T26	30		T27	77
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	466335	1			T26	17		T27	164		T29	207
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	381087	1			T25	138		T27	35		T28	18
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	534276	1			T25	146		T26	22		T27	98
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	2260992	1			T25	32		T26	90		T27	270
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	2176243	1			T25	190		T26	42		T27	51
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	540381	1			T25	126		T26	22		T27	89
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	468203	1			T26	18		T27	135		T28	3
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	383251	1			T25	142		T27	36		T28	13
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	530656	1			T25	114		T26	18		T27	60
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	2264143	1			T25	30		T26	82		T27	181
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	2175252	1			T25	161		T26	41		T27	24
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	538824	1			T25	122		T26	12		T27	53
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	468746	1			T26	26		T27	250		T29	288
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	381054	1			T25	168		T27	50		T29	42
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	531707	1			T25	123		T26	29		T27	83
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	2265332	1			T25	37		T26	77		T27	236
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	2174270	1			T25	190		T26	50		T27	54
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	538452	1			T25	90		T26	8		T27	133
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	464378	1			T26	39		T27	138		T29	268
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	383161	1			T25	165		T27	24		T29	21
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	534133	1			T25	122		T26	16		T27	56
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	2267184	1			T25	30		T26	64		T27	179
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	2174099	1			T25	182		T26	54		T27	37
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	537031	1			T25	128		T26	24		T27	82
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	466786	1			T26	32		T27	243		T28	4
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	380493	1			T25	108		T27	44		T28	8
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	534133	1			T25	156		T26	16		T27	56
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	2259835	1			T25	25		T26	86		T27	218
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	2180032	1			T25	182		T26	43		T27	48
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	540791	1			T25	146		T26	34		T27	79
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	467695	1			T26	16		T27	204		T28	1
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	379893	1			T25	105		T27	27		T28	13
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	531480	1			T25	146		T26	11		T27	65
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	2261918	1			T25	25		T26	86		T27	262
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	2178203	1			T25	166		T26	39		T27	45
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	541500	1			T25	125		T26	18		T27	127
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	466001	1			T26	28		T27	107		T29	383
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	381244	1			T25	128		T27	21		T28	4
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	530860	1			T25	160		T26	19		T27	79
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	2260118	1			T25	33		T26	78		T27	236
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	2173769	1			T25	168		T26	45		T27	35
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	536011	1			T25	127		T26	7		T27	111
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	469612	1			T26	34		T27	157		T29	251
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	385269	1			T25	114		T27	30		T29	33
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	534947	1			T25	162		T26	26		T27	72
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	2263041	1			T25	28		T26	67		T27	245
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	2174586	1			T25	197		T26	50		T27	28
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	534063	1			T25	127		T26	22		T27	97
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	470229	1			T26	28		T27	152		T29	305
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	383548	1			T25	118		T27	34		T29	27
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	534259	1			T25	134		T26	23		T27	85
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	2254790	1			T25	29		T26	67		T27	215
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	2187038	1			T25	209		T26	53		T27	46
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	535965	1			T25	122		T26	18		T27	89
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	469758	1			T26	30		T27	186		T29	291
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	382043	1			T25	138		T27	26		T29	28
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	530132	1			T25	106		T26	22		T27	79
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	2275510	1			T25	28		T26	54		T27	242
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	2164957	1			T25	174		T26	57		T27	43
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	535680	1			T25	130		T26	36		T27	54
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	466273	1			T26	19		T27	240		T28	5
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	384460	1			T25	142		T27	22		T28	19
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	532846	1			T25	130		T26	24		T27	40
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	2268275	1			T25	28		T26	67		T27	219
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	2170001	1			T25	169		T26	48		T27	46
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	536365	1			T25	135		T26	24		T27	64
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	467492	1			T26	18		T27	211		T28	6
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	384019	1			T25	130		T27	35		T28	16
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	533574	1			T25	142		T26	33		T27	66
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	2266807	1			T25	26		T26	78		T27	323
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	2175552	1			T25	186		T26	41		T27	56
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	532496	1			T25	104		T26	24		T27	65
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	468652	1			T26	15		T27	145		T29	249
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	385760	1			T25	148		T27	16		T29	18
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	530459	1			T25	140		T26	32		T27	36
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	2268599	1			T25	26		T26	72		T27	176
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	2172699	1			T25	160		T26	49		T27	32
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	537413	1			T25	158		T26	13		T27	126
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	468327	1			T26	28		T27	217		T28	4
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	380531	1			T25	134		T27	31		T28	27
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	532157	1			T25	126		T26	28		T27	59
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	2272739	1			T25	29		T26	81		T27	257
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	2168955	1			T25	184		T26	43		T27	57
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	532783	1			T25	128		T26	26		T27	56
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	470436	1			T26	22		T27	158		T28	5
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	383826	1			T25	151		T27	26		T28	20
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	530987	1			T25	112		T26	18		T27	87
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	2271782	1			T25	37		T26	79		T27	254
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	2164964	1			T25	143		T26	47		T27	30
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	537802	1			T25	132		T26	20		T27	75
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	469958	1			T26	28		T27	177		T29	362
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	384003	1			T25	152		T27	33		T29	41
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	531217	1			T25	140		T26	16		T27	72
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	2266551	1			T25	30		T26	76		T27	132
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	2180089	1			T25	179		T26	59		T27	25
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	539637	1			T25	140		T26	12		T27	54
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	464937	1			T26	27		T27	243		T28	4
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	379263	1			T25	151		T27	58		T28	21
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	529249	1			T25	104		T26	16		T27	129
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	2257383	1			T25	27		T26	76		T27	215
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	2184085	1			T25	142		T26	50		T27	44
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	537420	1			T25	168		T26	28		T27	80
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	468419	1			T26	12		T27	203		T29	304
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	382985	1			T25	130		T27	34		T29	35
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	529434	1			T25	137		T26	24		T27	65
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	2251427	1			T25	27		T26	71		T27	206
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	2187178	1			T25	155		T26	50		T27	46
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	536685	1			T25	154		T26	21		T27	121
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	469948	1			T26	12		T27	158		T29	327
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	382983	1			T25	146		T27	26		T29	39
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	531505	1			T25	122		T26	36		T27	84
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	2254945	1			T25	24		T26	73		T27	221
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	2183078	1			T25	142		T26	48		T27	43
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	536967	1			T25	150		T26	38		T27	94
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	470452	1			T26	13		T27	218		T28	1
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	382163	1			T25	154		T27	25		T28	25
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	532121	1			T25	134		T26	18		T27	40
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	2267766	1			T25	32		T26	83		T27	217
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	2176401	1			T25	158		T26	44		T27	43
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	535995	1			T25	126		T26	27		T27	74
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	469575	1			T26	14		T27	187		T29	264
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	381883	1			T25	150		T27	37		T29	30
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	528106	1			T25	138		T26	22		T27	83
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	2260675	1			T25	29		T26	82		T27	223
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	2183404	1			T25	164		T26	43		T27	41
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	537287	1			T25	155		T26	37		T27	90
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	467854	1			T26	12		T27	182		T29	310
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	380970	1			T25	106		T27	34		T28	13
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	529536	1			T25	150		T26	16		T27	71
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	2262857	1			T25	24		T26	90		T27	179
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	2174178	1			T25	157		T26	42		T27	22
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	535536	1			T25	144		T26	38		T27	74
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	470002	1			T26	10		T27	233		T28	10
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	384621	1			T25	147		T27	48		T28	20
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	532532	1			T25	132		T26	10		T27	85
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	2254202	1			T25	32		T26	71		T27	211
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	2184208	1			T25	193		T26	42		T27	47
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	539281	1			T25	140		T26	38		T27	95
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	470087	1			T26	21		T27	162		T29	177
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	382380	1			T25	127		T27	26		T29	30
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	529568	1			T25	112		T26	18		T27	100
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	2261469	1			T25	31		T26	80		T27	191
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	2183223	1			T25	187		T26	49		T27	34
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	535806	1			T25	142		T26	26		T27	71
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	466444	1			T26	17		T27	193		T28	11
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	382938	1			T25	102		T27	46		T28	33
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	529846	1			T25	142		T26	18		T27	106

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal