Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	6359726	1			T25	604		T26	190		T27	641
bins_for_gpio_bits[1]	6359726	1			T25	604		T26	190		T27	641
bins_for_gpio_bits[2]	6359726	1			T25	604		T26	190		T27	641
bins_for_gpio_bits[3]	6359726	1			T25	604		T26	190		T27	641
bins_for_gpio_bits[4]	6359726	1			T25	604		T26	190		T27	641
bins_for_gpio_bits[5]	6359726	1			T25	604		T26	190		T27	641
bins_for_gpio_bits[6]	6359726	1			T25	604		T26	190		T27	641
bins_for_gpio_bits[7]	6359726	1			T25	604		T26	190		T27	641
bins_for_gpio_bits[8]	6359726	1			T25	604		T26	190		T27	641
bins_for_gpio_bits[9]	6359726	1			T25	604		T26	190		T27	641
bins_for_gpio_bits[10]	6359726	1			T25	604		T26	190		T27	641
bins_for_gpio_bits[11]	6359726	1			T25	604		T26	190		T27	641
bins_for_gpio_bits[12]	6359726	1			T25	604		T26	190		T27	641
bins_for_gpio_bits[13]	6359726	1			T25	604		T26	190		T27	641
bins_for_gpio_bits[14]	6359726	1			T25	604		T26	190		T27	641
bins_for_gpio_bits[15]	6359726	1			T25	604		T26	190		T27	641
bins_for_gpio_bits[16]	6359726	1			T25	604		T26	190		T27	641
bins_for_gpio_bits[17]	6359726	1			T25	604		T26	190		T27	641
bins_for_gpio_bits[18]	6359726	1			T25	604		T26	190		T27	641
bins_for_gpio_bits[19]	6359726	1			T25	604		T26	190		T27	641
bins_for_gpio_bits[20]	6359726	1			T25	604		T26	190		T27	641
bins_for_gpio_bits[21]	6359726	1			T25	604		T26	190		T27	641
bins_for_gpio_bits[22]	6359726	1			T25	604		T26	190		T27	641
bins_for_gpio_bits[23]	6359726	1			T25	604		T26	190		T27	641
bins_for_gpio_bits[24]	6359726	1			T25	604		T26	190		T27	641
bins_for_gpio_bits[25]	6359726	1			T25	604		T26	190		T27	641
bins_for_gpio_bits[26]	6359726	1			T25	604		T26	190		T27	641
bins_for_gpio_bits[27]	6359726	1			T25	604		T26	190		T27	641
bins_for_gpio_bits[28]	6359726	1			T25	604		T26	190		T27	641
bins_for_gpio_bits[29]	6359726	1			T25	604		T26	190		T27	641
bins_for_gpio_bits[30]	6359726	1			T25	604		T26	190		T27	641
bins_for_gpio_bits[31]	6359726	1			T25	604		T26	190		T27	641

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

104582636

1

T25

5219

T26

3863

T27

15710

auto[1]

98928596

1

T25

14109

T26

2217

T27

4802

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

104576529

1

T25

5227

T26

3858

T27

15710

auto[1]

98934703

1

T25

14101

T26

2222

T27

4802

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	3185177	1			T25	113		T26	117		T27	485
bins_for_gpio_bits[0]	auto[0]	auto[1]	96764	1			T25	31		T26	6		T27	11
bins_for_gpio_bits[0]	auto[1]	auto[0]	96945	1			T25	31		T26	6		T27	11
bins_for_gpio_bits[0]	auto[1]	auto[1]	2980840	1			T25	429		T26	61		T27	134
bins_for_gpio_bits[1]	auto[0]	auto[0]	3171799	1			T25	110		T26	122		T27	486
bins_for_gpio_bits[1]	auto[0]	auto[1]	96049	1			T25	33		T26	4		T27	13
bins_for_gpio_bits[1]	auto[1]	auto[0]	96256	1			T25	33		T26	4		T27	13
bins_for_gpio_bits[1]	auto[1]	auto[1]	2995622	1			T25	428		T26	60		T27	129
bins_for_gpio_bits[2]	auto[0]	auto[0]	3171284	1			T25	160		T26	105		T27	439
bins_for_gpio_bits[2]	auto[0]	auto[1]	96835	1			T25	39		T26	7		T27	16
bins_for_gpio_bits[2]	auto[1]	auto[0]	97021	1			T25	38		T26	7		T27	16
bins_for_gpio_bits[2]	auto[1]	auto[1]	2994586	1			T25	367		T26	71		T27	170
bins_for_gpio_bits[3]	auto[0]	auto[0]	3152158	1			T25	155		T26	107		T27	502
bins_for_gpio_bits[3]	auto[0]	auto[1]	96513	1			T25	36		T26	6		T27	13
bins_for_gpio_bits[3]	auto[1]	auto[0]	96720	1			T25	36		T26	6		T27	13
bins_for_gpio_bits[3]	auto[1]	auto[1]	3014335	1			T25	377		T26	71		T27	113
bins_for_gpio_bits[4]	auto[0]	auto[0]	3169643	1			T25	128		T26	110		T27	466
bins_for_gpio_bits[4]	auto[0]	auto[1]	96272	1			T25	36		T26	9		T27	13
bins_for_gpio_bits[4]	auto[1]	auto[0]	96457	1			T25	35		T26	9		T27	13
bins_for_gpio_bits[4]	auto[1]	auto[1]	2997354	1			T25	405		T26	62		T27	149
bins_for_gpio_bits[5]	auto[0]	auto[0]	3162340	1			T25	115		T26	115		T27	450
bins_for_gpio_bits[5]	auto[0]	auto[1]	96580	1			T25	33		T26	7		T27	15
bins_for_gpio_bits[5]	auto[1]	auto[0]	96785	1			T25	32		T26	7		T27	15
bins_for_gpio_bits[5]	auto[1]	auto[1]	3004021	1			T25	424		T26	61		T27	161
bins_for_gpio_bits[6]	auto[0]	auto[0]	3176874	1			T25	120		T26	112		T27	458
bins_for_gpio_bits[6]	auto[0]	auto[1]	96206	1			T25	33		T26	5		T27	11
bins_for_gpio_bits[6]	auto[1]	auto[0]	96398	1			T25	33		T26	5		T27	11
bins_for_gpio_bits[6]	auto[1]	auto[1]	2990248	1			T25	418		T26	68		T27	161
bins_for_gpio_bits[7]	auto[0]	auto[0]	3171764	1			T25	128		T26	102		T27	456
bins_for_gpio_bits[7]	auto[0]	auto[1]	96054	1			T25	34		T26	7		T27	16
bins_for_gpio_bits[7]	auto[1]	auto[0]	96240	1			T25	34		T26	7		T27	16
bins_for_gpio_bits[7]	auto[1]	auto[1]	2995668	1			T25	408		T26	74		T27	153
bins_for_gpio_bits[8]	auto[0]	auto[0]	3172807	1			T25	125		T26	126		T27	485
bins_for_gpio_bits[8]	auto[0]	auto[1]	96579	1			T25	33		T26	4		T27	9
bins_for_gpio_bits[8]	auto[1]	auto[0]	96769	1			T25	33		T26	4		T27	9
bins_for_gpio_bits[8]	auto[1]	auto[1]	2993571	1			T25	413		T26	56		T27	138
bins_for_gpio_bits[9]	auto[0]	auto[0]	3174809	1			T25	125		T26	112		T27	466
bins_for_gpio_bits[9]	auto[0]	auto[1]	96746	1			T25	27		T26	7		T27	18
bins_for_gpio_bits[9]	auto[1]	auto[0]	96904	1			T25	27		T26	8		T27	18
bins_for_gpio_bits[9]	auto[1]	auto[1]	2991267	1			T25	425		T26	63		T27	139
bins_for_gpio_bits[10]	auto[0]	auto[0]	3171672	1			T25	99		T26	118		T27	497
bins_for_gpio_bits[10]	auto[0]	auto[1]	96278	1			T25	28		T26	6		T27	10
bins_for_gpio_bits[10]	auto[1]	auto[0]	96490	1			T25	28		T26	6		T27	10
bins_for_gpio_bits[10]	auto[1]	auto[1]	2995286	1			T25	449		T26	60		T27	124
bins_for_gpio_bits[11]	auto[0]	auto[0]	3174096	1			T25	122		T26	114		T27	495
bins_for_gpio_bits[11]	auto[0]	auto[1]	96729	1			T25	36		T26	6		T27	9
bins_for_gpio_bits[11]	auto[1]	auto[0]	96905	1			T25	36		T26	6		T27	9
bins_for_gpio_bits[11]	auto[1]	auto[1]	2991996	1			T25	410		T26	64		T27	128
bins_for_gpio_bits[12]	auto[0]	auto[0]	3171609	1			T25	137		T26	132		T27	489
bins_for_gpio_bits[12]	auto[0]	auto[1]	96514	1			T25	34		T26	3		T27	12
bins_for_gpio_bits[12]	auto[1]	auto[0]	96712	1			T25	34		T26	4		T27	12
bins_for_gpio_bits[12]	auto[1]	auto[1]	2994891	1			T25	399		T26	51		T27	128
bins_for_gpio_bits[13]	auto[0]	auto[0]	3173019	1			T25	117		T26	125		T27	482
bins_for_gpio_bits[13]	auto[0]	auto[1]	96220	1			T25	34		T26	6		T27	14
bins_for_gpio_bits[13]	auto[1]	auto[0]	96400	1			T25	33		T26	7		T27	14
bins_for_gpio_bits[13]	auto[1]	auto[1]	2994087	1			T25	420		T26	52		T27	131
bins_for_gpio_bits[14]	auto[0]	auto[0]	3168829	1			T25	124		T26	114		T27	490
bins_for_gpio_bits[14]	auto[0]	auto[1]	96726	1			T25	37		T26	5		T27	14
bins_for_gpio_bits[14]	auto[1]	auto[0]	96912	1			T25	36		T26	5		T27	14
bins_for_gpio_bits[14]	auto[1]	auto[1]	2997259	1			T25	407		T26	66		T27	123
bins_for_gpio_bits[15]	auto[0]	auto[0]	3170539	1			T25	124		T26	112		T27	476
bins_for_gpio_bits[15]	auto[0]	auto[1]	96603	1			T25	32		T26	4		T27	18
bins_for_gpio_bits[15]	auto[1]	auto[0]	96794	1			T25	31		T26	5		T27	18
bins_for_gpio_bits[15]	auto[1]	auto[1]	2995790	1			T25	417		T26	69		T27	129
bins_for_gpio_bits[16]	auto[0]	auto[0]	3164045	1			T25	120		T26	108		T27	475
bins_for_gpio_bits[16]	auto[0]	auto[1]	96288	1			T25	31		T26	7		T27	15
bins_for_gpio_bits[16]	auto[1]	auto[0]	96468	1			T25	31		T26	7		T27	15
bins_for_gpio_bits[16]	auto[1]	auto[1]	3002925	1			T25	422		T26	68		T27	136
bins_for_gpio_bits[17]	auto[0]	auto[0]	3181083	1			T25	123		T26	101		T27	528
bins_for_gpio_bits[17]	auto[0]	auto[1]	96191	1			T25	35		T26	8		T27	8
bins_for_gpio_bits[17]	auto[1]	auto[0]	96380	1			T25	35		T26	8		T27	8
bins_for_gpio_bits[17]	auto[1]	auto[1]	2986072	1			T25	411		T26	73		T27	97
bins_for_gpio_bits[18]	auto[0]	auto[0]	3175519	1			T25	127		T26	102		T27	479
bins_for_gpio_bits[18]	auto[0]	auto[1]	96386	1			T25	37		T26	6		T27	15
bins_for_gpio_bits[18]	auto[1]	auto[0]	96613	1			T25	36		T26	7		T27	15
bins_for_gpio_bits[18]	auto[1]	auto[1]	2991208	1			T25	404		T26	75		T27	132
bins_for_gpio_bits[19]	auto[0]	auto[0]	3171834	1			T25	96		T26	111		T27	525
bins_for_gpio_bits[19]	auto[0]	auto[1]	95946	1			T25	34		T26	6		T27	8
bins_for_gpio_bits[19]	auto[1]	auto[0]	96121	1			T25	34		T26	6		T27	8
bins_for_gpio_bits[19]	auto[1]	auto[1]	2995825	1			T25	440		T26	67		T27	100
bins_for_gpio_bits[20]	auto[0]	auto[0]	3177663	1			T25	147		T26	107		T27	507
bins_for_gpio_bits[20]	auto[0]	auto[1]	96462	1			T25	37		T26	6		T27	12
bins_for_gpio_bits[20]	auto[1]	auto[0]	96676	1			T25	37		T26	6		T27	12
bins_for_gpio_bits[20]	auto[1]	auto[1]	2988925	1			T25	383		T26	71		T27	110
bins_for_gpio_bits[21]	auto[0]	auto[0]	3179412	1			T25	125		T26	122		T27	460
bins_for_gpio_bits[21]	auto[0]	auto[1]	96316	1			T25	32		T26	7		T27	11
bins_for_gpio_bits[21]	auto[1]	auto[0]	96546	1			T25	32		T26	7		T27	11
bins_for_gpio_bits[21]	auto[1]	auto[1]	2987452	1			T25	415		T26	54		T27	159
bins_for_gpio_bits[22]	auto[0]	auto[0]	3182777	1			T25	137		T26	121		T27	492
bins_for_gpio_bits[22]	auto[0]	auto[1]	96571	1			T25	32		T26	6		T27	14
bins_for_gpio_bits[22]	auto[1]	auto[0]	96765	1			T25	32		T26	6		T27	14
bins_for_gpio_bits[22]	auto[1]	auto[1]	2983613	1			T25	403		T26	57		T27	121
bins_for_gpio_bits[23]	auto[0]	auto[0]	3174268	1			T25	135		T26	110		T27	413
bins_for_gpio_bits[23]	auto[0]	auto[1]	96676	1			T25	35		T26	5		T27	16
bins_for_gpio_bits[23]	auto[1]	auto[0]	96857	1			T25	35		T26	5		T27	16
bins_for_gpio_bits[23]	auto[1]	auto[1]	2991925	1			T25	399		T26	70		T27	196
bins_for_gpio_bits[24]	auto[0]	auto[0]	3166314	1			T25	160		T26	111		T27	480
bins_for_gpio_bits[24]	auto[0]	auto[1]	96732	1			T25	35		T26	5		T27	18
bins_for_gpio_bits[24]	auto[1]	auto[0]	96908	1			T25	35		T26	5		T27	18
bins_for_gpio_bits[24]	auto[1]	auto[1]	2999772	1			T25	374		T26	69		T27	125
bins_for_gpio_bits[25]	auto[0]	auto[0]	3160778	1			T25	144		T26	97		T27	472
bins_for_gpio_bits[25]	auto[0]	auto[1]	97097	1			T25	37		T26	7		T27	13
bins_for_gpio_bits[25]	auto[1]	auto[0]	97282	1			T25	37		T26	7		T27	13
bins_for_gpio_bits[25]	auto[1]	auto[1]	3004569	1			T25	386		T26	79		T27	143
bins_for_gpio_bits[26]	auto[0]	auto[0]	3165462	1			T25	141		T26	118		T27	521
bins_for_gpio_bits[26]	auto[0]	auto[1]	96709	1			T25	33		T26	6		T27	12
bins_for_gpio_bits[26]	auto[1]	auto[0]	96902	1			T25	33		T26	6		T27	12
bins_for_gpio_bits[26]	auto[1]	auto[1]	3000653	1			T25	397		T26	60		T27	96
bins_for_gpio_bits[27]	auto[0]	auto[0]	3177007	1			T25	126		T26	119		T27	463
bins_for_gpio_bits[27]	auto[0]	auto[1]	96146	1			T25	32		T26	5		T27	15
bins_for_gpio_bits[27]	auto[1]	auto[0]	96329	1			T25	32		T26	5		T27	15
bins_for_gpio_bits[27]	auto[1]	auto[1]	2990244	1			T25	414		T26	61		T27	148
bins_for_gpio_bits[28]	auto[0]	auto[0]	3169247	1			T25	148		T26	125		T27	481
bins_for_gpio_bits[28]	auto[0]	auto[1]	96382	1			T25	37		T26	6		T27	14
bins_for_gpio_bits[28]	auto[1]	auto[0]	96569	1			T25	36		T26	6		T27	14
bins_for_gpio_bits[28]	auto[1]	auto[1]	2997528	1			T25	383		T26	53		T27	132
bins_for_gpio_bits[29]	auto[0]	auto[0]	3171741	1			T25	133		T26	136		T27	471
bins_for_gpio_bits[29]	auto[0]	auto[1]	96460	1			T25	35		T26	2		T27	15
bins_for_gpio_bits[29]	auto[1]	auto[0]	96654	1			T25	35		T26	2		T27	15
bins_for_gpio_bits[29]	auto[1]	auto[1]	2994871	1			T25	401		T26	50		T27	140
bins_for_gpio_bits[30]	auto[0]	auto[0]	3166808	1			T25	139		T26	125		T27	455
bins_for_gpio_bits[30]	auto[0]	auto[1]	96583	1			T25	33		T26	5		T27	13
bins_for_gpio_bits[30]	auto[1]	auto[0]	96762	1			T25	33		T26	5		T27	13
bins_for_gpio_bits[30]	auto[1]	auto[1]	2999573	1			T25	399		T26	55		T27	160
bins_for_gpio_bits[31]	auto[0]	auto[0]	3167259	1			T25	133		T26	117		T27	436
bins_for_gpio_bits[31]	auto[0]	auto[1]	96280	1			T25	40		T26	6		T27	19
bins_for_gpio_bits[31]	auto[1]	auto[0]	96460	1			T25	40		T26	6		T27	19
bins_for_gpio_bits[31]	auto[1]	auto[1]	2999727	1			T25	391		T26	61		T27	167