Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4301146 |
1 |
|
|
T25 |
332 |
|
T26 |
144 |
|
T27 |
334 |
| auto[1] |
2082305 |
1 |
|
|
T30 |
183 |
|
T31 |
742 |
|
T32 |
36 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6126421 |
1 |
|
|
T25 |
332 |
|
T26 |
144 |
|
T27 |
334 |
| auto[1] |
257030 |
1 |
|
|
T30 |
7 |
|
T31 |
125 |
|
T1 |
10 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4314647 |
1 |
|
|
T25 |
332 |
|
T26 |
144 |
|
T27 |
334 |
| auto[1] |
2068804 |
1 |
|
|
T30 |
86 |
|
T31 |
708 |
|
T32 |
32 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
903764 |
1 |
|
|
T30 |
8 |
|
T31 |
289 |
|
T32 |
13 |
| auto[1] |
auto[0] |
auto[1] |
127860 |
1 |
|
|
T30 |
2 |
|
T31 |
66 |
|
T1 |
6 |
| auto[1] |
auto[1] |
auto[0] |
908010 |
1 |
|
|
T30 |
71 |
|
T31 |
294 |
|
T32 |
19 |
| auto[1] |
auto[1] |
auto[1] |
129170 |
1 |
|
|
T30 |
5 |
|
T31 |
59 |
|
T1 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |