Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4323942 |
1 |
|
|
T25 |
332 |
|
T26 |
144 |
|
T27 |
334 |
| auto[1] |
2059509 |
1 |
|
|
T30 |
136 |
|
T31 |
797 |
|
T32 |
28 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6126431 |
1 |
|
|
T25 |
332 |
|
T26 |
144 |
|
T27 |
334 |
| auto[1] |
257020 |
1 |
|
|
T30 |
10 |
|
T31 |
143 |
|
T1 |
7 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4319544 |
1 |
|
|
T25 |
332 |
|
T26 |
144 |
|
T27 |
334 |
| auto[1] |
2063907 |
1 |
|
|
T30 |
122 |
|
T31 |
809 |
|
T32 |
7 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
909883 |
1 |
|
|
T30 |
34 |
|
T31 |
359 |
|
T32 |
4 |
| auto[1] |
auto[0] |
auto[1] |
129460 |
1 |
|
|
T30 |
3 |
|
T31 |
82 |
|
T1 |
2 |
| auto[1] |
auto[1] |
auto[0] |
897004 |
1 |
|
|
T30 |
78 |
|
T31 |
307 |
|
T32 |
3 |
| auto[1] |
auto[1] |
auto[1] |
127560 |
1 |
|
|
T30 |
7 |
|
T31 |
61 |
|
T1 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |