Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4310883 |
1 |
|
|
T25 |
332 |
|
T26 |
144 |
|
T27 |
334 |
| auto[1] |
2072568 |
1 |
|
|
T30 |
102 |
|
T31 |
605 |
|
T32 |
51 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5374767 |
1 |
|
|
T25 |
332 |
|
T26 |
144 |
|
T27 |
334 |
| auto[1] |
1008684 |
1 |
|
|
T30 |
80 |
|
T31 |
446 |
|
T32 |
18 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4305822 |
1 |
|
|
T25 |
332 |
|
T26 |
144 |
|
T27 |
334 |
| auto[1] |
2077629 |
1 |
|
|
T30 |
129 |
|
T31 |
855 |
|
T32 |
44 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
535879 |
1 |
|
|
T30 |
33 |
|
T31 |
246 |
|
T32 |
5 |
| auto[1] |
auto[0] |
auto[1] |
506283 |
1 |
|
|
T30 |
41 |
|
T31 |
267 |
|
T32 |
5 |
| auto[1] |
auto[1] |
auto[0] |
533066 |
1 |
|
|
T30 |
16 |
|
T31 |
163 |
|
T32 |
21 |
| auto[1] |
auto[1] |
auto[1] |
502401 |
1 |
|
|
T30 |
39 |
|
T31 |
179 |
|
T32 |
13 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |