Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4314372 |
1 |
|
|
T25 |
332 |
|
T26 |
144 |
|
T27 |
334 |
| auto[1] |
2069079 |
1 |
|
|
T30 |
186 |
|
T31 |
687 |
|
T32 |
27 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5382170 |
1 |
|
|
T25 |
332 |
|
T26 |
144 |
|
T27 |
334 |
| auto[1] |
1001281 |
1 |
|
|
T30 |
39 |
|
T31 |
349 |
|
T32 |
22 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4322662 |
1 |
|
|
T25 |
332 |
|
T26 |
144 |
|
T27 |
334 |
| auto[1] |
2060789 |
1 |
|
|
T30 |
99 |
|
T31 |
696 |
|
T32 |
28 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
529420 |
1 |
|
|
T30 |
23 |
|
T31 |
176 |
|
T32 |
3 |
| auto[1] |
auto[0] |
auto[1] |
503215 |
1 |
|
|
T30 |
7 |
|
T31 |
196 |
|
T32 |
14 |
| auto[1] |
auto[1] |
auto[0] |
530088 |
1 |
|
|
T30 |
37 |
|
T31 |
171 |
|
T32 |
3 |
| auto[1] |
auto[1] |
auto[1] |
498066 |
1 |
|
|
T30 |
32 |
|
T31 |
153 |
|
T32 |
8 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |