Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4322929 |
1 |
|
|
T25 |
332 |
|
T26 |
144 |
|
T27 |
334 |
| auto[1] |
2060522 |
1 |
|
|
T30 |
171 |
|
T31 |
746 |
|
T32 |
36 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5369240 |
1 |
|
|
T25 |
332 |
|
T26 |
144 |
|
T27 |
334 |
| auto[1] |
1014211 |
1 |
|
|
T30 |
40 |
|
T31 |
399 |
|
T32 |
10 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4300512 |
1 |
|
|
T25 |
332 |
|
T26 |
144 |
|
T27 |
334 |
| auto[1] |
2082939 |
1 |
|
|
T30 |
77 |
|
T31 |
795 |
|
T32 |
34 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
542185 |
1 |
|
|
T30 |
15 |
|
T31 |
140 |
|
T32 |
17 |
| auto[1] |
auto[0] |
auto[1] |
513525 |
1 |
|
|
T30 |
8 |
|
T31 |
184 |
|
T1 |
32 |
| auto[1] |
auto[1] |
auto[0] |
526543 |
1 |
|
|
T30 |
22 |
|
T31 |
256 |
|
T32 |
7 |
| auto[1] |
auto[1] |
auto[1] |
500686 |
1 |
|
|
T30 |
32 |
|
T31 |
215 |
|
T32 |
10 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |