Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4315636 |
1 |
|
|
T25 |
332 |
|
T26 |
144 |
|
T27 |
334 |
auto[1] |
2067815 |
1 |
|
|
T30 |
138 |
|
T31 |
657 |
|
T32 |
32 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
5381010 |
1 |
|
|
T25 |
332 |
|
T26 |
144 |
|
T27 |
334 |
auto[1] |
1002441 |
1 |
|
|
T30 |
47 |
|
T31 |
335 |
|
T32 |
16 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4318485 |
1 |
|
|
T25 |
332 |
|
T26 |
144 |
|
T27 |
334 |
auto[1] |
2064966 |
1 |
|
|
T30 |
125 |
|
T31 |
629 |
|
T32 |
21 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
533220 |
1 |
|
|
T30 |
36 |
|
T31 |
176 |
|
T32 |
5 |
auto[1] |
auto[0] |
auto[1] |
502349 |
1 |
|
|
T30 |
27 |
|
T31 |
227 |
|
T32 |
5 |
auto[1] |
auto[1] |
auto[0] |
529305 |
1 |
|
|
T30 |
42 |
|
T31 |
118 |
|
T1 |
91 |
auto[1] |
auto[1] |
auto[1] |
500092 |
1 |
|
|
T30 |
20 |
|
T31 |
108 |
|
T32 |
11 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4309190 |
1 |
|
|
T25 |
332 |
|
T26 |
144 |
|
T27 |
334 |
auto[1] |
2074261 |
1 |
|
|
T30 |
148 |
|
T31 |
606 |
|
T32 |
42 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
5322494 |
1 |
|
|
T25 |
332 |
|
T26 |
144 |
|
T27 |
334 |
auto[1] |
1060957 |
1 |
|
|
T30 |
90 |
|
T31 |
430 |
|
T32 |
15 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4318082 |
1 |
|
|
T25 |
332 |
|
T26 |
144 |
|
T27 |
334 |
auto[1] |
2065369 |
1 |
|
|
T30 |
153 |
|
T31 |
848 |
|
T32 |
29 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
501065 |
1 |
|
|
T30 |
36 |
|
T31 |
236 |
|
T32 |
3 |
auto[1] |
auto[0] |
auto[1] |
527112 |
1 |
|
|
T30 |
39 |
|
T31 |
237 |
|
T32 |
11 |
auto[1] |
auto[1] |
auto[0] |
503347 |
1 |
|
|
T30 |
27 |
|
T31 |
182 |
|
T32 |
11 |
auto[1] |
auto[1] |
auto[1] |
533845 |
1 |
|
|
T30 |
51 |
|
T31 |
193 |
|
T32 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4317459 |
1 |
|
|
T25 |
332 |
|
T26 |
144 |
|
T27 |
334 |
auto[1] |
2065992 |
1 |
|
|
T30 |
101 |
|
T31 |
865 |
|
T32 |
31 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
5319775 |
1 |
|
|
T25 |
332 |
|
T26 |
144 |
|
T27 |
334 |
auto[1] |
1063676 |
1 |
|
|
T30 |
68 |
|
T31 |
275 |
|
T32 |
15 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4311334 |
1 |
|
|
T25 |
332 |
|
T26 |
144 |
|
T27 |
334 |
auto[1] |
2072117 |
1 |
|
|
T30 |
118 |
|
T31 |
567 |
|
T32 |
17 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
508141 |
1 |
|
|
T30 |
26 |
|
T31 |
102 |
|
T1 |
14 |
auto[1] |
auto[0] |
auto[1] |
534888 |
1 |
|
|
T30 |
42 |
|
T31 |
93 |
|
T32 |
6 |
auto[1] |
auto[1] |
auto[0] |
500300 |
1 |
|
|
T30 |
24 |
|
T31 |
190 |
|
T32 |
2 |
auto[1] |
auto[1] |
auto[1] |
528788 |
1 |
|
|
T30 |
26 |
|
T31 |
182 |
|
T32 |
9 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4326372 |
1 |
|
|
T25 |
332 |
|
T26 |
144 |
|
T27 |
334 |
auto[1] |
2057079 |
1 |
|
|
T30 |
150 |
|
T31 |
1027 |
|
T32 |
47 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
5313197 |
1 |
|
|
T25 |
332 |
|
T26 |
144 |
|
T27 |
334 |
auto[1] |
1070254 |
1 |
|
|
T30 |
47 |
|
T31 |
387 |
|
T32 |
8 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4303502 |
1 |
|
|
T25 |
332 |
|
T26 |
144 |
|
T27 |
334 |
auto[1] |
2079949 |
1 |
|
|
T30 |
99 |
|
T31 |
732 |
|
T32 |
17 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
509496 |
1 |
|
|
T30 |
18 |
|
T31 |
148 |
|
T1 |
78 |
auto[1] |
auto[0] |
auto[1] |
542114 |
1 |
|
|
T30 |
14 |
|
T31 |
161 |
|
T32 |
2 |
auto[1] |
auto[1] |
auto[0] |
500199 |
1 |
|
|
T30 |
34 |
|
T31 |
197 |
|
T32 |
9 |
auto[1] |
auto[1] |
auto[1] |
528140 |
1 |
|
|
T30 |
33 |
|
T31 |
226 |
|
T32 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4310883 |
1 |
|
|
T25 |
332 |
|
T26 |
144 |
|
T27 |
334 |
auto[1] |
2072568 |
1 |
|
|
T30 |
102 |
|
T31 |
605 |
|
T32 |
51 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
5315404 |
1 |
|
|
T25 |
332 |
|
T26 |
144 |
|
T27 |
334 |
auto[1] |
1068047 |
1 |
|
|
T30 |
32 |
|
T31 |
357 |
|
T32 |
19 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4298003 |
1 |
|
|
T25 |
332 |
|
T26 |
144 |
|
T27 |
334 |
auto[1] |
2085448 |
1 |
|
|
T30 |
75 |
|
T31 |
774 |
|
T32 |
20 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
512625 |
1 |
|
|
T30 |
19 |
|
T31 |
219 |
|
T1 |
57 |
auto[1] |
auto[0] |
auto[1] |
532250 |
1 |
|
|
T30 |
19 |
|
T31 |
177 |
|
T32 |
6 |
auto[1] |
auto[1] |
auto[0] |
504776 |
1 |
|
|
T30 |
24 |
|
T31 |
198 |
|
T32 |
1 |
auto[1] |
auto[1] |
auto[1] |
535797 |
1 |
|
|
T30 |
13 |
|
T31 |
180 |
|
T32 |
13 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4314372 |
1 |
|
|
T25 |
332 |
|
T26 |
144 |
|
T27 |
334 |
auto[1] |
2069079 |
1 |
|
|
T30 |
186 |
|
T31 |
687 |
|
T32 |
27 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
5315852 |
1 |
|
|
T25 |
332 |
|
T26 |
144 |
|
T27 |
334 |
auto[1] |
1067599 |
1 |
|
|
T30 |
77 |
|
T31 |
347 |
|
T1 |
305 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4311956 |
1 |
|
|
T25 |
332 |
|
T26 |
144 |
|
T27 |
334 |
auto[1] |
2071495 |
1 |
|
|
T30 |
127 |
|
T31 |
727 |
|
T32 |
10 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
502915 |
1 |
|
|
T30 |
10 |
|
T31 |
204 |
|
T32 |
6 |
auto[1] |
auto[0] |
auto[1] |
535341 |
1 |
|
|
T30 |
20 |
|
T31 |
178 |
|
T1 |
109 |
auto[1] |
auto[1] |
auto[0] |
500981 |
1 |
|
|
T30 |
40 |
|
T31 |
176 |
|
T32 |
4 |
auto[1] |
auto[1] |
auto[1] |
532258 |
1 |
|
|
T30 |
57 |
|
T31 |
169 |
|
T1 |
196 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4304364 |
1 |
|
|
T25 |
332 |
|
T26 |
144 |
|
T27 |
334 |
auto[1] |
2079087 |
1 |
|
|
T30 |
102 |
|
T31 |
498 |
|
T32 |
35 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
5323497 |
1 |
|
|
T25 |
332 |
|
T26 |
144 |
|
T27 |
334 |
auto[1] |
1059954 |
1 |
|
|
T30 |
58 |
|
T31 |
385 |
|
T32 |
10 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4318870 |
1 |
|
|
T25 |
332 |
|
T26 |
144 |
|
T27 |
334 |
auto[1] |
2064581 |
1 |
|
|
T30 |
102 |
|
T31 |
784 |
|
T32 |
28 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
505259 |
1 |
|
|
T30 |
27 |
|
T31 |
250 |
|
T32 |
15 |
auto[1] |
auto[0] |
auto[1] |
534156 |
1 |
|
|
T30 |
27 |
|
T31 |
242 |
|
T32 |
1 |
auto[1] |
auto[1] |
auto[0] |
499368 |
1 |
|
|
T30 |
17 |
|
T31 |
149 |
|
T32 |
3 |
auto[1] |
auto[1] |
auto[1] |
525798 |
1 |
|
|
T30 |
31 |
|
T31 |
143 |
|
T32 |
9 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4322929 |
1 |
|
|
T25 |
332 |
|
T26 |
144 |
|
T27 |
334 |
auto[1] |
2060522 |
1 |
|
|
T30 |
171 |
|
T31 |
746 |
|
T32 |
36 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
5322168 |
1 |
|
|
T25 |
332 |
|
T26 |
144 |
|
T27 |
334 |
auto[1] |
1061283 |
1 |
|
|
T30 |
52 |
|
T31 |
345 |
|
T32 |
18 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4311596 |
1 |
|
|
T25 |
332 |
|
T26 |
144 |
|
T27 |
334 |
auto[1] |
2071855 |
1 |
|
|
T30 |
105 |
|
T31 |
617 |
|
T32 |
18 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
502766 |
1 |
|
|
T30 |
14 |
|
T31 |
110 |
|
T1 |
64 |
auto[1] |
auto[0] |
auto[1] |
528311 |
1 |
|
|
T30 |
28 |
|
T31 |
115 |
|
T32 |
14 |
auto[1] |
auto[1] |
auto[0] |
507806 |
1 |
|
|
T30 |
39 |
|
T31 |
162 |
|
T1 |
87 |
auto[1] |
auto[1] |
auto[1] |
532972 |
1 |
|
|
T30 |
24 |
|
T31 |
230 |
|
T32 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4326265 |
1 |
|
|
T25 |
332 |
|
T26 |
144 |
|
T27 |
334 |
auto[1] |
2057186 |
1 |
|
|
T30 |
116 |
|
T31 |
433 |
|
T32 |
17 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
5322826 |
1 |
|
|
T25 |
332 |
|
T26 |
144 |
|
T27 |
334 |
auto[1] |
1060625 |
1 |
|
|
T30 |
33 |
|
T31 |
326 |
|
T32 |
1 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4308587 |
1 |
|
|
T25 |
332 |
|
T26 |
144 |
|
T27 |
334 |
auto[1] |
2074864 |
1 |
|
|
T30 |
98 |
|
T31 |
658 |
|
T32 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
516895 |
1 |
|
|
T30 |
37 |
|
T31 |
223 |
|
T1 |
20 |
auto[1] |
auto[0] |
auto[1] |
538448 |
1 |
|
|
T30 |
20 |
|
T31 |
212 |
|
T32 |
1 |
auto[1] |
auto[1] |
auto[0] |
497344 |
1 |
|
|
T30 |
28 |
|
T31 |
109 |
|
T1 |
109 |
auto[1] |
auto[1] |
auto[1] |
522177 |
1 |
|
|
T30 |
13 |
|
T31 |
114 |
|
T1 |
154 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4313202 |
1 |
|
|
T25 |
332 |
|
T26 |
144 |
|
T27 |
334 |
auto[1] |
2070249 |
1 |
|
|
T30 |
106 |
|
T31 |
853 |
|
T32 |
22 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
5320584 |
1 |
|
|
T25 |
332 |
|
T26 |
144 |
|
T27 |
334 |
auto[1] |
1062867 |
1 |
|
|
T30 |
59 |
|
T31 |
425 |
|
T32 |
15 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4310097 |
1 |
|
|
T25 |
332 |
|
T26 |
144 |
|
T27 |
334 |
auto[1] |
2073354 |
1 |
|
|
T30 |
107 |
|
T31 |
858 |
|
T32 |
27 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
507969 |
1 |
|
|
T30 |
22 |
|
T31 |
218 |
|
T32 |
3 |
auto[1] |
auto[0] |
auto[1] |
534300 |
1 |
|
|
T30 |
40 |
|
T31 |
221 |
|
T32 |
9 |
auto[1] |
auto[1] |
auto[0] |
502518 |
1 |
|
|
T30 |
26 |
|
T31 |
215 |
|
T32 |
9 |
auto[1] |
auto[1] |
auto[1] |
528567 |
1 |
|
|
T30 |
19 |
|
T31 |
204 |
|
T32 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4325262 |
1 |
|
|
T25 |
332 |
|
T26 |
144 |
|
T27 |
334 |
auto[1] |
2058189 |
1 |
|
|
T30 |
108 |
|
T31 |
861 |
|
T32 |
23 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
5315264 |
1 |
|
|
T25 |
332 |
|
T26 |
144 |
|
T27 |
334 |
auto[1] |
1068187 |
1 |
|
|
T30 |
59 |
|
T31 |
301 |
|
T1 |
356 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4306427 |
1 |
|
|
T25 |
332 |
|
T26 |
144 |
|
T27 |
334 |
auto[1] |
2077024 |
1 |
|
|
T30 |
134 |
|
T31 |
545 |
|
T32 |
8 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
503873 |
1 |
|
|
T30 |
42 |
|
T31 |
130 |
|
T32 |
4 |
auto[1] |
auto[0] |
auto[1] |
537724 |
1 |
|
|
T30 |
35 |
|
T31 |
152 |
|
T1 |
241 |
auto[1] |
auto[1] |
auto[0] |
504964 |
1 |
|
|
T30 |
33 |
|
T31 |
114 |
|
T32 |
4 |
auto[1] |
auto[1] |
auto[1] |
530463 |
1 |
|
|
T30 |
24 |
|
T31 |
149 |
|
T1 |
115 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4308042 |
1 |
|
|
T25 |
332 |
|
T26 |
144 |
|
T27 |
334 |
auto[1] |
2075409 |
1 |
|
|
T30 |
63 |
|
T31 |
651 |
|
T32 |
30 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
5324214 |
1 |
|
|
T25 |
332 |
|
T26 |
144 |
|
T27 |
334 |
auto[1] |
1059237 |
1 |
|
|
T30 |
75 |
|
T31 |
446 |
|
T32 |
9 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4318972 |
1 |
|
|
T25 |
332 |
|
T26 |
144 |
|
T27 |
334 |
auto[1] |
2064479 |
1 |
|
|
T30 |
141 |
|
T31 |
947 |
|
T32 |
24 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
501881 |
1 |
|
|
T30 |
44 |
|
T31 |
314 |
|
T32 |
5 |
auto[1] |
auto[0] |
auto[1] |
531902 |
1 |
|
|
T30 |
59 |
|
T31 |
288 |
|
T32 |
9 |
auto[1] |
auto[1] |
auto[0] |
503361 |
1 |
|
|
T30 |
22 |
|
T31 |
187 |
|
T32 |
10 |
auto[1] |
auto[1] |
auto[1] |
527335 |
1 |
|
|
T30 |
16 |
|
T31 |
158 |
|
T1 |
185 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4311082 |
1 |
|
|
T25 |
332 |
|
T26 |
144 |
|
T27 |
334 |
auto[1] |
2072369 |
1 |
|
|
T30 |
95 |
|
T31 |
734 |
|
T32 |
47 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
5320124 |
1 |
|
|
T25 |
332 |
|
T26 |
144 |
|
T27 |
334 |
auto[1] |
1063327 |
1 |
|
|
T30 |
96 |
|
T31 |
342 |
|
T32 |
4 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4312044 |
1 |
|
|
T25 |
332 |
|
T26 |
144 |
|
T27 |
334 |
auto[1] |
2071407 |
1 |
|
|
T30 |
182 |
|
T31 |
715 |
|
T32 |
29 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
503328 |
1 |
|
|
T30 |
57 |
|
T31 |
160 |
|
T32 |
8 |
auto[1] |
auto[0] |
auto[1] |
532528 |
1 |
|
|
T30 |
48 |
|
T31 |
168 |
|
T1 |
189 |
auto[1] |
auto[1] |
auto[0] |
504752 |
1 |
|
|
T30 |
29 |
|
T31 |
213 |
|
T32 |
17 |
auto[1] |
auto[1] |
auto[1] |
530799 |
1 |
|
|
T30 |
48 |
|
T31 |
174 |
|
T32 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |