Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	6427713	1			T41	137		T42	98		T43	118
all_values[1]	6427713	1			T41	137		T42	98		T43	118
all_values[2]	6427713	1			T41	137		T42	98		T43	118
all_values[3]	6427713	1			T41	137		T42	98		T43	118
all_values[4]	6427713	1			T41	137		T42	98		T43	118
all_values[5]	6427713	1			T41	137		T42	98		T43	118
all_values[6]	6427713	1			T41	137		T42	98		T43	118
all_values[7]	6427713	1			T41	137		T42	98		T43	118
all_values[8]	6427713	1			T41	137		T42	98		T43	118
all_values[9]	6427713	1			T41	137		T42	98		T43	118
all_values[10]	6427713	1			T41	137		T42	98		T43	118
all_values[11]	6427713	1			T41	137		T42	98		T43	118
all_values[12]	6427713	1			T41	137		T42	98		T43	118
all_values[13]	6427713	1			T41	137		T42	98		T43	118
all_values[14]	6427713	1			T41	137		T42	98		T43	118
all_values[15]	6427713	1			T41	137		T42	98		T43	118
all_values[16]	6427713	1			T41	137		T42	98		T43	118
all_values[17]	6427713	1			T41	137		T42	98		T43	118
all_values[18]	6427713	1			T41	137		T42	98		T43	118
all_values[19]	6427713	1			T41	137		T42	98		T43	118
all_values[20]	6427713	1			T41	137		T42	98		T43	118
all_values[21]	6427713	1			T41	137		T42	98		T43	118
all_values[22]	6427713	1			T41	137		T42	98		T43	118
all_values[23]	6427713	1			T41	137		T42	98		T43	118
all_values[24]	6427713	1			T41	137		T42	98		T43	118
all_values[25]	6427713	1			T41	137		T42	98		T43	118
all_values[26]	6427713	1			T41	137		T42	98		T43	118
all_values[27]	6427713	1			T41	137		T42	98		T43	118
all_values[28]	6427713	1			T41	137		T42	98		T43	118
all_values[29]	6427713	1			T41	137		T42	98		T43	118
all_values[30]	6427713	1			T41	137		T42	98		T43	118
all_values[31]	6427713	1			T41	137		T42	98		T43	118

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

137593452

1

T41

4384

T42

3136

T43

3776

auto[1]

68093364

1

T1

665

T12

6198

T2

683

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

83006407

1

T41

4384

T42

3136

T43

3776

auto[1]

122680409

1

T1

566

T12

9623

T2

794

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2375599	1			T41	137		T42	98		T43	118
all_values[0]	auto[0]	auto[1]	1915106	1			T1	4		T12	141		T2	5
all_values[0]	auto[1]	auto[0]	218680	1			T1	23		T12	22		T2	6
all_values[0]	auto[1]	auto[1]	1918328	1			T1	7		T12	183		T2	13
all_values[1]	auto[0]	auto[0]	2380704	1			T41	137		T42	98		T43	118
all_values[1]	auto[0]	auto[1]	1919293	1			T1	14		T12	189		T2	17
all_values[1]	auto[1]	auto[0]	214896	1			T1	6		T12	40		T2	18
all_values[1]	auto[1]	auto[1]	1912820	1			T12	110		T34	133		T39	975
all_values[2]	auto[0]	auto[0]	2374526	1			T41	137		T42	98		T43	118
all_values[2]	auto[0]	auto[1]	1932968	1			T1	11		T12	175		T2	7
all_values[2]	auto[1]	auto[0]	218397	1			T1	13		T12	38		T2	16
all_values[2]	auto[1]	auto[1]	1901822	1			T1	1		T12	126		T2	20
all_values[3]	auto[0]	auto[0]	2373764	1			T41	137		T42	98		T43	118
all_values[3]	auto[0]	auto[1]	1916132	1			T1	7		T12	168		T2	22
all_values[3]	auto[1]	auto[0]	217368	1			T1	15		T12	41		T2	2
all_values[3]	auto[1]	auto[1]	1920449	1			T1	14		T12	136		T34	174
all_values[4]	auto[0]	auto[0]	2378290	1			T41	137		T42	98		T43	118
all_values[4]	auto[0]	auto[1]	1925632	1			T1	17		T12	59		T2	7
all_values[4]	auto[1]	auto[0]	216424	1			T1	13		T12	76		T2	10
all_values[4]	auto[1]	auto[1]	1907367	1			T1	3		T12	182		T2	16
all_values[5]	auto[0]	auto[0]	2375550	1			T41	137		T42	98		T43	118
all_values[5]	auto[0]	auto[1]	1913667	1			T1	11		T12	164		T2	17
all_values[5]	auto[1]	auto[0]	217250	1			T1	19		T12	26		T2	14
all_values[5]	auto[1]	auto[1]	1921246	1			T1	8		T12	143		T2	5
all_values[6]	auto[0]	auto[0]	2378169	1			T41	137		T42	98		T43	118
all_values[6]	auto[0]	auto[1]	1940410	1			T1	13		T12	132		T2	13
all_values[6]	auto[1]	auto[0]	215918	1			T1	22		T12	31		T2	16
all_values[6]	auto[1]	auto[1]	1893216	1			T1	6		T12	171		T2	9
all_values[7]	auto[0]	auto[0]	2374654	1			T41	137		T42	98		T43	118
all_values[7]	auto[0]	auto[1]	1922177	1			T1	2		T12	162		T2	29
all_values[7]	auto[1]	auto[0]	215854	1			T1	14		T12	54		T2	7
all_values[7]	auto[1]	auto[1]	1915028	1			T1	20		T12	120		T34	108
all_values[8]	auto[0]	auto[0]	2380163	1			T41	137		T42	98		T43	118
all_values[8]	auto[0]	auto[1]	1933753	1			T1	9		T12	144		T2	31
all_values[8]	auto[1]	auto[0]	216659	1			T1	11		T12	45		T2	9
all_values[8]	auto[1]	auto[1]	1897138	1			T1	16		T12	155		T2	1
all_values[9]	auto[0]	auto[0]	2376586	1			T41	137		T42	98		T43	118
all_values[9]	auto[0]	auto[1]	1929695	1			T1	4		T12	133		T2	6
all_values[9]	auto[1]	auto[0]	216450	1			T1	27		T12	50		T2	14
all_values[9]	auto[1]	auto[1]	1904982	1			T1	4		T12	171		T2	17
all_values[10]	auto[0]	auto[0]	2373295	1			T41	137		T42	98		T43	118
all_values[10]	auto[0]	auto[1]	1936662	1			T1	15		T12	174		T2	20
all_values[10]	auto[1]	auto[0]	215622	1			T1	10		T12	17		T2	4
all_values[10]	auto[1]	auto[1]	1902134	1			T1	7		T12	155		T2	8
all_values[11]	auto[0]	auto[0]	2378999	1			T41	137		T42	98		T43	118
all_values[11]	auto[0]	auto[1]	1923817	1			T1	9		T12	204		T2	15
all_values[11]	auto[1]	auto[0]	219991	1			T1	17		T12	36		T2	22
all_values[11]	auto[1]	auto[1]	1904906	1			T1	10		T12	112		T2	3
all_values[12]	auto[0]	auto[0]	2376474	1			T41	137		T42	98		T43	118
all_values[12]	auto[0]	auto[1]	1933387	1			T1	17		T12	142		T2	21
all_values[12]	auto[1]	auto[0]	215734	1			T1	15		T12	29		T2	5
all_values[12]	auto[1]	auto[1]	1902118	1			T1	6		T12	195		T2	7
all_values[13]	auto[0]	auto[0]	2377848	1			T41	137		T42	98		T43	118
all_values[13]	auto[0]	auto[1]	1913915	1			T1	5		T12	117		T2	29
all_values[13]	auto[1]	auto[0]	223097	1			T1	10		T12	47		T2	6
all_values[13]	auto[1]	auto[1]	1912853	1			T1	17		T12	170		T2	6
all_values[14]	auto[0]	auto[0]	2375797	1			T41	137		T42	98		T43	118
all_values[14]	auto[0]	auto[1]	1947531	1			T1	4		T12	131		T2	12
all_values[14]	auto[1]	auto[0]	216547	1			T1	11		T12	27		T2	14
all_values[14]	auto[1]	auto[1]	1887838	1			T1	10		T12	163		T2	17
all_values[15]	auto[0]	auto[0]	2373092	1			T41	137		T42	98		T43	118
all_values[15]	auto[0]	auto[1]	1911277	1			T1	10		T12	144		T2	11
all_values[15]	auto[1]	auto[0]	212934	1			T1	24		T12	15		T2	17
all_values[15]	auto[1]	auto[1]	1930410	1			T1	8		T12	169		T2	8
all_values[16]	auto[0]	auto[0]	2379352	1			T41	137		T42	98		T43	118
all_values[16]	auto[0]	auto[1]	1910192	1			T1	5		T12	119		T2	8
all_values[16]	auto[1]	auto[0]	213307	1			T1	21		T12	37		T2	12
all_values[16]	auto[1]	auto[1]	1924862	1			T1	3		T12	173		T2	4
all_values[17]	auto[0]	auto[0]	2377892	1			T41	137		T42	98		T43	118
all_values[17]	auto[0]	auto[1]	1918613	1			T1	4		T12	152		T2	22
all_values[17]	auto[1]	auto[0]	216849	1			T1	16		T12	63		T2	4
all_values[17]	auto[1]	auto[1]	1914359	1			T1	14		T12	122		T2	8
all_values[18]	auto[0]	auto[0]	2377482	1			T41	137		T42	98		T43	118
all_values[18]	auto[0]	auto[1]	1910157	1			T1	14		T12	140		T2	9
all_values[18]	auto[1]	auto[0]	218706	1			T1	6		T12	9		T2	12
all_values[18]	auto[1]	auto[1]	1921368	1			T1	6		T12	161		T2	24
all_values[19]	auto[0]	auto[0]	2378163	1			T41	137		T42	98		T43	118
all_values[19]	auto[0]	auto[1]	1917004	1			T1	17		T12	142		T2	16
all_values[19]	auto[1]	auto[0]	224091	1			T1	4		T12	33		T2	17
all_values[19]	auto[1]	auto[1]	1908455	1			T1	1		T12	156		T2	6
all_values[20]	auto[0]	auto[0]	2374073	1			T41	137		T42	98		T43	118
all_values[20]	auto[0]	auto[1]	1915351	1			T1	16		T12	138		T2	7
all_values[20]	auto[1]	auto[0]	217977	1			T1	17		T12	55		T2	21
all_values[20]	auto[1]	auto[1]	1920312	1			T12	148		T2	16		T34	141
all_values[21]	auto[0]	auto[0]	2376980	1			T41	137		T42	98		T43	118
all_values[21]	auto[0]	auto[1]	1919898	1			T1	14		T12	141		T2	30
all_values[21]	auto[1]	auto[0]	218575	1			T1	17		T12	64		T2	4
all_values[21]	auto[1]	auto[1]	1912260	1			T1	4		T12	124		T2	3
all_values[22]	auto[0]	auto[0]	2376285	1			T41	137		T42	98		T43	118
all_values[22]	auto[0]	auto[1]	1942183	1			T1	7		T12	108		T2	9
all_values[22]	auto[1]	auto[0]	218569	1			T1	12		T12	47		T2	14
all_values[22]	auto[1]	auto[1]	1890676	1			T1	11		T12	189		T2	3
all_values[23]	auto[0]	auto[0]	2375059	1			T41	137		T42	98		T43	118
all_values[23]	auto[0]	auto[1]	1910473	1			T1	6		T12	144		T2	8
all_values[23]	auto[1]	auto[0]	218928	1			T1	11		T12	32		T2	17
all_values[23]	auto[1]	auto[1]	1923253	1			T1	14		T12	133		T2	6
all_values[24]	auto[0]	auto[0]	2374776	1			T41	137		T42	98		T43	118
all_values[24]	auto[0]	auto[1]	1913807	1			T1	19		T12	125		T2	10
all_values[24]	auto[1]	auto[0]	216833	1			T1	13		T12	40		T2	12
all_values[24]	auto[1]	auto[1]	1922297	1			T1	3		T12	169		T2	19
all_values[25]	auto[0]	auto[0]	2380817	1			T41	137		T42	98		T43	118
all_values[25]	auto[0]	auto[1]	1921452	1			T1	3		T12	141		T2	28
all_values[25]	auto[1]	auto[0]	212595	1			T1	20		T12	53		T2	7
all_values[25]	auto[1]	auto[1]	1912849	1			T1	1		T12	142		T34	141
all_values[26]	auto[0]	auto[0]	2378232	1			T41	137		T42	98		T43	118
all_values[26]	auto[0]	auto[1]	1932198	1			T1	10		T12	100		T2	13
all_values[26]	auto[1]	auto[0]	214910	1			T1	7		T12	25		T2	10
all_values[26]	auto[1]	auto[1]	1902373	1			T1	6		T12	217		T2	21
all_values[27]	auto[0]	auto[0]	2379456	1			T41	137		T42	98		T43	118
all_values[27]	auto[0]	auto[1]	1918258	1			T1	9		T12	185		T2	3
all_values[27]	auto[1]	auto[0]	217554	1			T1	8		T12	23		T2	25
all_values[27]	auto[1]	auto[1]	1912445	1			T1	11		T12	132		T2	15
all_values[28]	auto[0]	auto[0]	2376601	1			T41	137		T42	98		T43	118
all_values[28]	auto[0]	auto[1]	1912165	1			T1	13		T12	137		T2	13
all_values[28]	auto[1]	auto[0]	219009	1			T1	8		T12	38		T2	14
all_values[28]	auto[1]	auto[1]	1919938	1			T1	6		T12	154		T2	14
all_values[29]	auto[0]	auto[0]	2373261	1			T41	137		T42	98		T43	118
all_values[29]	auto[0]	auto[1]	1929192	1			T1	10		T12	154		T2	24
all_values[29]	auto[1]	auto[0]	217684	1			T1	4		T12	3		T2	14
all_values[29]	auto[1]	auto[1]	1907576	1			T1	6		T12	187		T2	6
all_values[30]	auto[0]	auto[0]	2376309	1			T41	137		T42	98		T43	118
all_values[30]	auto[0]	auto[1]	1932930	1			T1	17		T12	165		T2	18
all_values[30]	auto[1]	auto[0]	219875	1			T1	4		T12	15		T2	9
all_values[30]	auto[1]	auto[1]	1898599	1			T1	3		T12	172		T2	13
all_values[31]	auto[0]	auto[0]	2375542	1			T41	137		T42	98		T43	118
all_values[31]	auto[0]	auto[1]	1920367	1			T1	10		T12	125		T2	11
all_values[31]	auto[1]	auto[0]	215334	1			T1	7		T12	39		T2	8
all_values[31]	auto[1]	auto[1]	1916470	1			T1	14		T12	188		T2	15