Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	1589121	1			T41	1		T42	1		T43	1
all_pins[1]	1589121	1			T41	1		T42	1		T43	1
all_pins[2]	1589121	1			T41	1		T42	1		T43	1
all_pins[3]	1589121	1			T41	1		T42	1		T43	1
all_pins[4]	1589121	1			T41	1		T42	1		T43	1
all_pins[5]	1589121	1			T41	1		T42	1		T43	1
all_pins[6]	1589121	1			T41	1		T42	1		T43	1
all_pins[7]	1589121	1			T41	1		T42	1		T43	1
all_pins[8]	1589121	1			T41	1		T42	1		T43	1
all_pins[9]	1589121	1			T41	1		T42	1		T43	1
all_pins[10]	1589121	1			T41	1		T42	1		T43	1
all_pins[11]	1589121	1			T41	1		T42	1		T43	1
all_pins[12]	1589121	1			T41	1		T42	1		T43	1
all_pins[13]	1589121	1			T41	1		T42	1		T43	1
all_pins[14]	1589121	1			T41	1		T42	1		T43	1
all_pins[15]	1589121	1			T41	1		T42	1		T43	1
all_pins[16]	1589121	1			T41	1		T42	1		T43	1
all_pins[17]	1589121	1			T41	1		T42	1		T43	1
all_pins[18]	1589121	1			T41	1		T42	1		T43	1
all_pins[19]	1589121	1			T41	1		T42	1		T43	1
all_pins[20]	1589121	1			T41	1		T42	1		T43	1
all_pins[21]	1589121	1			T41	1		T42	1		T43	1
all_pins[22]	1589121	1			T41	1		T42	1		T43	1
all_pins[23]	1589121	1			T41	1		T42	1		T43	1
all_pins[24]	1589121	1			T41	1		T42	1		T43	1
all_pins[25]	1589121	1			T41	1		T42	1		T43	1
all_pins[26]	1589121	1			T41	1		T42	1		T43	1
all_pins[27]	1589121	1			T41	1		T42	1		T43	1
all_pins[28]	1589121	1			T41	1		T42	1		T43	1
all_pins[29]	1589121	1			T41	1		T42	1		T43	1
all_pins[30]	1589121	1			T41	1		T42	1		T43	1
all_pins[31]	1589121	1			T41	1		T42	1		T43	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	31632603	1			T41	32		T42	32		T43	32
values[0x1]	19219269	1			T1	182		T11	212		T12	2989
transitions[0x0=>0x1]	11513818	1			T1	119		T11	112		T12	1829
transitions[0x1=>0x0]	11513665	1			T1	119		T11	111		T12	1828

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	986170	1			T41	1		T42	1		T43	1
all_pins[0]	values[0x1]	602951	1			T1	7		T11	7		T12	106
all_pins[0]	transitions[0x0=>0x1]	371894	1			T1	5		T11	5		T12	64
all_pins[0]	transitions[0x1=>0x0]	371260	1			T1	9		T11	1		T12	72
all_pins[1]	values[0x0]	992797	1			T41	1		T42	1		T43	1
all_pins[1]	values[0x1]	596324	1			T11	6		T12	74		T34	74
all_pins[1]	transitions[0x0=>0x1]	355073	1			T11	4		T12	39		T34	58
all_pins[1]	transitions[0x1=>0x0]	361700	1			T1	7		T11	5		T12	71
all_pins[2]	values[0x0]	990179	1			T41	1		T42	1		T43	1
all_pins[2]	values[0x1]	598942	1			T1	1		T11	5		T12	74
all_pins[2]	transitions[0x0=>0x1]	359553	1			T1	1		T11	4		T12	52
all_pins[2]	transitions[0x1=>0x0]	356935	1			T11	5		T12	52		T34	49
all_pins[3]	values[0x0]	983453	1			T41	1		T42	1		T43	1
all_pins[3]	values[0x1]	605668	1			T1	12		T11	2		T12	75
all_pins[3]	transitions[0x0=>0x1]	363350	1			T1	11		T12	55		T34	63
all_pins[3]	transitions[0x1=>0x0]	356624	1			T11	3		T12	54		T2	11
all_pins[4]	values[0x0]	988957	1			T41	1		T42	1		T43	1
all_pins[4]	values[0x1]	600164	1			T1	3		T11	10		T12	103
all_pins[4]	transitions[0x0=>0x1]	357813	1			T1	2		T11	8		T12	78
all_pins[4]	transitions[0x1=>0x0]	363317	1			T1	11		T12	50		T34	51
all_pins[5]	values[0x0]	985446	1			T41	1		T42	1		T43	1
all_pins[5]	values[0x1]	603675	1			T1	6		T11	3		T12	87
all_pins[5]	transitions[0x0=>0x1]	361510	1			T1	5		T11	1		T12	47
all_pins[5]	transitions[0x1=>0x0]	357999	1			T1	2		T11	8		T12	63
all_pins[6]	values[0x0]	990566	1			T41	1		T42	1		T43	1
all_pins[6]	values[0x1]	598555	1			T1	4		T11	8		T12	117
all_pins[6]	transitions[0x0=>0x1]	357784	1			T1	4		T11	7		T12	75
all_pins[6]	transitions[0x1=>0x0]	362904	1			T1	6		T11	2		T12	45
all_pins[7]	values[0x0]	989567	1			T41	1		T42	1		T43	1
all_pins[7]	values[0x1]	599554	1			T1	15		T11	9		T12	70
all_pins[7]	transitions[0x0=>0x1]	358817	1			T1	13		T11	3		T12	43
all_pins[7]	transitions[0x1=>0x0]	357818	1			T1	2		T11	2		T12	90
all_pins[8]	values[0x0]	988441	1			T41	1		T42	1		T43	1
all_pins[8]	values[0x1]	600680	1			T1	11		T11	9		T12	88
all_pins[8]	transitions[0x0=>0x1]	360608	1			T11	4		T12	63		T2	1
all_pins[8]	transitions[0x1=>0x0]	359482	1			T1	4		T11	4		T12	45
all_pins[9]	values[0x0]	987060	1			T41	1		T42	1		T43	1
all_pins[9]	values[0x1]	602061	1			T1	3		T11	10		T12	99
all_pins[9]	transitions[0x0=>0x1]	360091	1			T1	1		T11	5		T12	66
all_pins[9]	transitions[0x1=>0x0]	358710	1			T1	9		T11	4		T12	55
all_pins[10]	values[0x0]	986541	1			T41	1		T42	1		T43	1
all_pins[10]	values[0x1]	602580	1			T1	4		T11	9		T12	89
all_pins[10]	transitions[0x0=>0x1]	360807	1			T1	2		T11	1		T12	53
all_pins[10]	transitions[0x1=>0x0]	360288	1			T1	1		T11	2		T12	63
all_pins[11]	values[0x0]	991359	1			T41	1		T42	1		T43	1
all_pins[11]	values[0x1]	597762	1			T1	10		T11	6		T12	66
all_pins[11]	transitions[0x0=>0x1]	357462	1			T1	8		T11	3		T12	48
all_pins[11]	transitions[0x1=>0x0]	362280	1			T1	2		T11	6		T12	71
all_pins[12]	values[0x0]	988650	1			T41	1		T42	1		T43	1
all_pins[12]	values[0x1]	600471	1			T1	5		T11	10		T12	117
all_pins[12]	transitions[0x0=>0x1]	359923	1			T1	2		T11	7		T12	83
all_pins[12]	transitions[0x1=>0x0]	357214	1			T1	7		T11	3		T12	32
all_pins[13]	values[0x0]	986344	1			T41	1		T42	1		T43	1
all_pins[13]	values[0x1]	602777	1			T1	14		T11	6		T12	100
all_pins[13]	transitions[0x0=>0x1]	359830	1			T1	9		T11	2		T12	48
all_pins[13]	transitions[0x1=>0x0]	357524	1			T11	6		T12	65		T2	2
all_pins[14]	values[0x0]	995075	1			T41	1		T42	1		T43	1
all_pins[14]	values[0x1]	594046	1			T1	8		T11	6		T12	87
all_pins[14]	transitions[0x0=>0x1]	355393	1			T1	1		T11	3		T12	41
all_pins[14]	transitions[0x1=>0x0]	364124	1			T1	7		T11	3		T12	54
all_pins[15]	values[0x0]	984620	1			T41	1		T42	1		T43	1
all_pins[15]	values[0x1]	604501	1			T1	7		T11	2		T12	105
all_pins[15]	transitions[0x0=>0x1]	363935	1			T1	1		T11	1		T12	64
all_pins[15]	transitions[0x1=>0x0]	353480	1			T1	2		T11	5		T12	46
all_pins[16]	values[0x0]	987376	1			T41	1		T42	1		T43	1
all_pins[16]	values[0x1]	601745	1			T1	1		T11	5		T12	102
all_pins[16]	transitions[0x0=>0x1]	359517	1			T1	1		T11	5		T12	63
all_pins[16]	transitions[0x1=>0x0]	362273	1			T1	7		T11	2		T12	66
all_pins[17]	values[0x0]	990329	1			T41	1		T42	1		T43	1
all_pins[17]	values[0x1]	598792	1			T1	10		T11	8		T12	70
all_pins[17]	transitions[0x0=>0x1]	357983	1			T1	9		T11	5		T12	59
all_pins[17]	transitions[0x1=>0x0]	360936	1			T11	2		T12	91		T34	49
all_pins[18]	values[0x0]	987624	1			T41	1		T42	1		T43	1
all_pins[18]	values[0x1]	601497	1			T1	4		T11	6		T12	96
all_pins[18]	transitions[0x0=>0x1]	359619	1			T1	2		T11	3		T12	54
all_pins[18]	transitions[0x1=>0x0]	356914	1			T1	8		T11	5		T12	28
all_pins[19]	values[0x0]	990813	1			T41	1		T42	1		T43	1
all_pins[19]	values[0x1]	598308	1			T1	1		T11	7		T12	95
all_pins[19]	transitions[0x0=>0x1]	358129	1			T1	1		T11	5		T12	64
all_pins[19]	transitions[0x1=>0x0]	361318	1			T1	4		T11	4		T12	65
all_pins[20]	values[0x0]	987593	1			T41	1		T42	1		T43	1
all_pins[20]	values[0x1]	601528	1			T11	7		T12	88		T2	13
all_pins[20]	transitions[0x0=>0x1]	362794	1			T11	2		T12	48		T2	13
all_pins[20]	transitions[0x1=>0x0]	359574	1			T1	1		T11	2		T12	55
all_pins[21]	values[0x0]	990074	1			T41	1		T42	1		T43	1
all_pins[21]	values[0x1]	599047	1			T1	2		T11	6		T12	74
all_pins[21]	transitions[0x0=>0x1]	358476	1			T1	2		T11	3		T12	44
all_pins[21]	transitions[0x1=>0x0]	360957	1			T11	4		T12	58		T2	12
all_pins[22]	values[0x0]	990173	1			T41	1		T42	1		T43	1
all_pins[22]	values[0x1]	598948	1			T1	7		T11	10		T12	107
all_pins[22]	transitions[0x0=>0x1]	358694	1			T1	6		T11	7		T12	74
all_pins[22]	transitions[0x1=>0x0]	358793	1			T1	1		T11	3		T12	41
all_pins[23]	values[0x0]	986771	1			T41	1		T42	1		T43	1
all_pins[23]	values[0x1]	602350	1			T1	11		T11	4		T12	75
all_pins[23]	transitions[0x0=>0x1]	360550	1			T1	6		T11	2		T12	22
all_pins[23]	transitions[0x1=>0x0]	357148	1			T1	2		T11	8		T12	54
all_pins[24]	values[0x0]	988093	1			T41	1		T42	1		T43	1
all_pins[24]	values[0x1]	601028	1			T1	3		T11	5		T12	97
all_pins[24]	transitions[0x0=>0x1]	358375	1			T1	1		T11	3		T12	62
all_pins[24]	transitions[0x1=>0x0]	359697	1			T1	9		T11	2		T12	40
all_pins[25]	values[0x0]	991111	1			T41	1		T42	1		T43	1
all_pins[25]	values[0x1]	598010	1			T1	1		T11	7		T12	86
all_pins[25]	transitions[0x0=>0x1]	358018	1			T11	4		T12	47		T34	55
all_pins[25]	transitions[0x1=>0x0]	361036	1			T1	2		T11	2		T12	58
all_pins[26]	values[0x0]	989617	1			T41	1		T42	1		T43	1
all_pins[26]	values[0x1]	599504	1			T1	3		T11	6		T12	141
all_pins[26]	transitions[0x0=>0x1]	359958	1			T1	3		T11	1		T12	79
all_pins[26]	transitions[0x1=>0x0]	358464	1			T1	1		T11	2		T12	24
all_pins[27]	values[0x0]	987570	1			T41	1		T42	1		T43	1
all_pins[27]	values[0x1]	601551	1			T1	9		T11	5		T12	81
all_pins[27]	transitions[0x0=>0x1]	361003	1			T1	8		T11	2		T12	42
all_pins[27]	transitions[0x1=>0x0]	358956	1			T1	2		T11	3		T12	102
all_pins[28]	values[0x0]	985215	1			T41	1		T42	1		T43	1
all_pins[28]	values[0x1]	603906	1			T1	4		T11	8		T12	89
all_pins[28]	transitions[0x0=>0x1]	360437	1			T1	4		T11	5		T12	53
all_pins[28]	transitions[0x1=>0x0]	358082	1			T1	9		T11	2		T12	45
all_pins[29]	values[0x0]	989954	1			T41	1		T42	1		T43	1
all_pins[29]	values[0x1]	599167	1			T1	3		T11	9		T12	107
all_pins[29]	transitions[0x0=>0x1]	356421	1			T1	1		T11	2		T12	69
all_pins[29]	transitions[0x1=>0x0]	361160	1			T1	2		T11	1		T12	51
all_pins[30]	values[0x0]	988414	1			T41	1		T42	1		T43	1
all_pins[30]	values[0x1]	600707	1			T1	2		T11	7		T12	109
all_pins[30]	transitions[0x0=>0x1]	361346	1			T1	1		T11	4		T12	56
all_pins[30]	transitions[0x1=>0x0]	359806	1			T1	2		T11	6		T12	54
all_pins[31]	values[0x0]	986651	1			T41	1		T42	1		T43	1
all_pins[31]	values[0x1]	602470	1			T1	11		T11	4		T12	115
all_pins[31]	transitions[0x0=>0x1]	358655	1			T1	9		T11	1		T12	74
all_pins[31]	transitions[0x1=>0x0]	356892	1			T11	4		T12	68		T2	4