Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	6427713	1			T41	137		T42	98		T43	118
all_values[1]	6427713	1			T41	137		T42	98		T43	118
all_values[2]	6427713	1			T41	137		T42	98		T43	118
all_values[3]	6427713	1			T41	137		T42	98		T43	118
all_values[4]	6427713	1			T41	137		T42	98		T43	118
all_values[5]	6427713	1			T41	137		T42	98		T43	118
all_values[6]	6427713	1			T41	137		T42	98		T43	118
all_values[7]	6427713	1			T41	137		T42	98		T43	118
all_values[8]	6427713	1			T41	137		T42	98		T43	118
all_values[9]	6427713	1			T41	137		T42	98		T43	118
all_values[10]	6427713	1			T41	137		T42	98		T43	118
all_values[11]	6427713	1			T41	137		T42	98		T43	118
all_values[12]	6427713	1			T41	137		T42	98		T43	118
all_values[13]	6427713	1			T41	137		T42	98		T43	118
all_values[14]	6427713	1			T41	137		T42	98		T43	118
all_values[15]	6427713	1			T41	137		T42	98		T43	118
all_values[16]	6427713	1			T41	137		T42	98		T43	118
all_values[17]	6427713	1			T41	137		T42	98		T43	118
all_values[18]	6427713	1			T41	137		T42	98		T43	118
all_values[19]	6427713	1			T41	137		T42	98		T43	118
all_values[20]	6427713	1			T41	137		T42	98		T43	118
all_values[21]	6427713	1			T41	137		T42	98		T43	118
all_values[22]	6427713	1			T41	137		T42	98		T43	118
all_values[23]	6427713	1			T41	137		T42	98		T43	118
all_values[24]	6427713	1			T41	137		T42	98		T43	118
all_values[25]	6427713	1			T41	137		T42	98		T43	118
all_values[26]	6427713	1			T41	137		T42	98		T43	118
all_values[27]	6427713	1			T41	137		T42	98		T43	118
all_values[28]	6427713	1			T41	137		T42	98		T43	118
all_values[29]	6427713	1			T41	137		T42	98		T43	118
all_values[30]	6427713	1			T41	137		T42	98		T43	118
all_values[31]	6427713	1			T41	137		T42	98		T43	118

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

137593452

1

T41

4384

T42

3136

T43

3776

auto[1]

68093364

1

T1

665

T12

6198

T2

683

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

83006407

1

T41

4384

T42

3136

T43

3776

auto[1]

122680409

1

T1

566

T12

9623

T2

794

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

203799149

1

T41

4384

T42

3136

T43

3776

auto[1]

1887667

1

T1

112

T2

140

T3

902

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	2375599	1			T41	137		T42	98		T43	118
all_values[0]	auto[0]	auto[0]	auto[1]	1885715	1			T1	3		T12	141		T2	2
all_values[0]	auto[0]	auto[1]	auto[0]	218680	1			T1	23		T12	22		T2	6
all_values[0]	auto[0]	auto[1]	auto[1]	1888889	1			T1	5		T12	183		T2	12
all_values[0]	auto[1]	auto[0]	auto[1]	29391	1			T1	1		T2	3		T3	18
all_values[0]	auto[1]	auto[1]	auto[1]	29439	1			T1	2		T2	1		T3	14
all_values[1]	auto[0]	auto[0]	auto[0]	2380704	1			T41	137		T42	98		T43	118
all_values[1]	auto[0]	auto[0]	auto[1]	1889636	1			T1	11		T12	189		T2	11
all_values[1]	auto[0]	auto[1]	auto[0]	214896	1			T1	6		T12	40		T2	18
all_values[1]	auto[0]	auto[1]	auto[1]	1883614	1			T12	110		T34	133		T39	975
all_values[1]	auto[1]	auto[0]	auto[1]	29657	1			T1	3		T2	6		T3	23
all_values[1]	auto[1]	auto[1]	auto[1]	29206	1			T3	5		T47	1		T4	11
all_values[2]	auto[0]	auto[0]	auto[0]	2374526	1			T41	137		T42	98		T43	118
all_values[2]	auto[0]	auto[0]	auto[1]	1903141	1			T1	7		T12	175		T2	5
all_values[2]	auto[0]	auto[1]	auto[0]	218397	1			T1	13		T12	38		T2	16
all_values[2]	auto[0]	auto[1]	auto[1]	1872449	1			T12	126		T2	18		T34	118
all_values[2]	auto[1]	auto[0]	auto[1]	29827	1			T1	4		T2	2		T3	18
all_values[2]	auto[1]	auto[1]	auto[1]	29373	1			T1	1		T2	2		T3	10
all_values[3]	auto[0]	auto[0]	auto[0]	2373764	1			T41	137		T42	98		T43	118
all_values[3]	auto[0]	auto[0]	auto[1]	1886598	1			T1	4		T12	168		T2	18
all_values[3]	auto[0]	auto[1]	auto[0]	217368	1			T1	15		T12	41		T2	2
all_values[3]	auto[0]	auto[1]	auto[1]	1890832	1			T1	13		T12	136		T34	174
all_values[3]	auto[1]	auto[0]	auto[1]	29534	1			T1	3		T2	4		T3	15
all_values[3]	auto[1]	auto[1]	auto[1]	29617	1			T1	1		T3	12		T4	19
all_values[4]	auto[0]	auto[0]	auto[0]	2378290	1			T41	137		T42	98		T43	118
all_values[4]	auto[0]	auto[0]	auto[1]	1895545	1			T1	14		T12	59		T2	3
all_values[4]	auto[0]	auto[1]	auto[0]	216424	1			T1	13		T12	76		T2	10
all_values[4]	auto[0]	auto[1]	auto[1]	1878265	1			T1	1		T12	182		T2	15
all_values[4]	auto[1]	auto[0]	auto[1]	30087	1			T1	3		T2	4		T3	15
all_values[4]	auto[1]	auto[1]	auto[1]	29102	1			T1	2		T2	1		T3	7
all_values[5]	auto[0]	auto[0]	auto[0]	2375550	1			T41	137		T42	98		T43	118
all_values[5]	auto[0]	auto[0]	auto[1]	1884127	1			T1	8		T12	164		T2	11
all_values[5]	auto[0]	auto[1]	auto[0]	217250	1			T1	19		T12	26		T2	14
all_values[5]	auto[0]	auto[1]	auto[1]	1891917	1			T1	7		T12	143		T2	5
all_values[5]	auto[1]	auto[0]	auto[1]	29540	1			T1	3		T2	6		T3	14
all_values[5]	auto[1]	auto[1]	auto[1]	29329	1			T1	1		T3	11		T47	2
all_values[6]	auto[0]	auto[0]	auto[0]	2378169	1			T41	137		T42	98		T43	118
all_values[6]	auto[0]	auto[0]	auto[1]	1910619	1			T1	12		T12	132		T2	10
all_values[6]	auto[0]	auto[1]	auto[0]	215918	1			T1	22		T12	31		T2	16
all_values[6]	auto[0]	auto[1]	auto[1]	1863957	1			T1	4		T12	171		T2	8
all_values[6]	auto[1]	auto[0]	auto[1]	29791	1			T1	1		T2	3		T3	20
all_values[6]	auto[1]	auto[1]	auto[1]	29259	1			T1	2		T2	1		T3	7
all_values[7]	auto[0]	auto[0]	auto[0]	2374654	1			T41	137		T42	98		T43	118
all_values[7]	auto[0]	auto[0]	auto[1]	1892200	1			T1	1		T12	162		T2	25
all_values[7]	auto[0]	auto[1]	auto[0]	215854	1			T1	14		T12	54		T2	7
all_values[7]	auto[0]	auto[1]	auto[1]	1885630	1			T1	20		T12	120		T34	108
all_values[7]	auto[1]	auto[0]	auto[1]	29977	1			T1	1		T2	4		T3	13
all_values[7]	auto[1]	auto[1]	auto[1]	29398	1			T3	14		T47	1		T4	15
all_values[8]	auto[0]	auto[0]	auto[0]	2380163	1			T41	137		T42	98		T43	118
all_values[8]	auto[0]	auto[0]	auto[1]	1903974	1			T1	7		T12	144		T2	28
all_values[8]	auto[0]	auto[1]	auto[0]	216659	1			T1	11		T12	45		T2	9
all_values[8]	auto[0]	auto[1]	auto[1]	1867944	1			T1	14		T12	155		T2	1
all_values[8]	auto[1]	auto[0]	auto[1]	29779	1			T1	2		T2	3		T3	20
all_values[8]	auto[1]	auto[1]	auto[1]	29194	1			T1	2		T3	11		T4	19
all_values[9]	auto[0]	auto[0]	auto[0]	2376586	1			T41	137		T42	98		T43	118
all_values[9]	auto[0]	auto[0]	auto[1]	1899777	1			T1	2		T12	133		T2	5
all_values[9]	auto[0]	auto[1]	auto[0]	216450	1			T1	27		T12	50		T2	14
all_values[9]	auto[0]	auto[1]	auto[1]	1875742	1			T1	3		T12	171		T2	15
all_values[9]	auto[1]	auto[0]	auto[1]	29918	1			T1	2		T2	1		T3	18
all_values[9]	auto[1]	auto[1]	auto[1]	29240	1			T1	1		T2	2		T3	13
all_values[10]	auto[0]	auto[0]	auto[0]	2373295	1			T41	137		T42	98		T43	118
all_values[10]	auto[0]	auto[0]	auto[1]	1906844	1			T1	11		T12	174		T2	16
all_values[10]	auto[0]	auto[1]	auto[0]	215622	1			T1	10		T12	17		T2	4
all_values[10]	auto[0]	auto[1]	auto[1]	1873016	1			T1	7		T12	155		T2	8
all_values[10]	auto[1]	auto[0]	auto[1]	29818	1			T1	4		T2	4		T3	13
all_values[10]	auto[1]	auto[1]	auto[1]	29118	1			T3	12		T47	1		T4	11
all_values[11]	auto[0]	auto[0]	auto[0]	2378999	1			T41	137		T42	98		T43	118
all_values[11]	auto[0]	auto[0]	auto[1]	1894017	1			T1	6		T12	204		T2	14
all_values[11]	auto[0]	auto[1]	auto[0]	219991	1			T1	17		T12	36		T2	22
all_values[11]	auto[0]	auto[1]	auto[1]	1875525	1			T1	9		T12	112		T2	3
all_values[11]	auto[1]	auto[0]	auto[1]	29800	1			T1	3		T2	1		T3	10
all_values[11]	auto[1]	auto[1]	auto[1]	29381	1			T1	1		T3	18		T47	2
all_values[12]	auto[0]	auto[0]	auto[0]	2376474	1			T41	137		T42	98		T43	118
all_values[12]	auto[0]	auto[0]	auto[1]	1903635	1			T1	14		T12	142		T2	17
all_values[12]	auto[0]	auto[1]	auto[0]	215734	1			T1	15		T12	29		T2	5
all_values[12]	auto[0]	auto[1]	auto[1]	1873120	1			T1	5		T12	195		T2	5
all_values[12]	auto[1]	auto[0]	auto[1]	29752	1			T1	3		T2	4		T3	10
all_values[12]	auto[1]	auto[1]	auto[1]	28998	1			T1	1		T2	2		T3	14
all_values[13]	auto[0]	auto[0]	auto[0]	2377848	1			T41	137		T42	98		T43	118
all_values[13]	auto[0]	auto[0]	auto[1]	1884425	1			T1	4		T12	117		T2	22
all_values[13]	auto[0]	auto[1]	auto[0]	223097	1			T1	10		T12	47		T2	6
all_values[13]	auto[0]	auto[1]	auto[1]	1883418	1			T1	17		T12	170		T2	6
all_values[13]	auto[1]	auto[0]	auto[1]	29490	1			T1	1		T2	7		T3	15
all_values[13]	auto[1]	auto[1]	auto[1]	29435	1			T3	15		T47	2		T4	23
all_values[14]	auto[0]	auto[0]	auto[0]	2375797	1			T41	137		T42	98		T43	118
all_values[14]	auto[0]	auto[0]	auto[1]	1917777	1			T1	4		T12	131		T2	11
all_values[14]	auto[0]	auto[1]	auto[0]	216547	1			T1	11		T12	27		T2	14
all_values[14]	auto[0]	auto[1]	auto[1]	1858757	1			T1	8		T12	163		T2	13
all_values[14]	auto[1]	auto[0]	auto[1]	29754	1			T2	1		T3	10		T47	1
all_values[14]	auto[1]	auto[1]	auto[1]	29081	1			T1	2		T2	4		T3	19
all_values[15]	auto[0]	auto[0]	auto[0]	2373092	1			T41	137		T42	98		T43	118
all_values[15]	auto[0]	auto[0]	auto[1]	1881656	1			T1	9		T12	144		T2	8
all_values[15]	auto[0]	auto[1]	auto[0]	212934	1			T1	24		T12	15		T2	17
all_values[15]	auto[0]	auto[1]	auto[1]	1900948	1			T1	6		T12	169		T2	8
all_values[15]	auto[1]	auto[0]	auto[1]	29621	1			T1	1		T2	3		T3	14
all_values[15]	auto[1]	auto[1]	auto[1]	29462	1			T1	2		T3	10		T47	1
all_values[16]	auto[0]	auto[0]	auto[0]	2379352	1			T41	137		T42	98		T43	118
all_values[16]	auto[0]	auto[0]	auto[1]	1880518	1			T1	4		T12	119		T2	4
all_values[16]	auto[0]	auto[1]	auto[0]	213307	1			T1	21		T12	37		T2	12
all_values[16]	auto[0]	auto[1]	auto[1]	1895590	1			T1	2		T12	173		T2	4
all_values[16]	auto[1]	auto[0]	auto[1]	29674	1			T1	1		T2	4		T3	14
all_values[16]	auto[1]	auto[1]	auto[1]	29272	1			T1	1		T3	15		T47	2
all_values[17]	auto[0]	auto[0]	auto[0]	2377892	1			T41	137		T42	98		T43	118
all_values[17]	auto[0]	auto[0]	auto[1]	1888658	1			T1	2		T12	152		T2	18
all_values[17]	auto[0]	auto[1]	auto[0]	216849	1			T1	16		T12	63		T2	4
all_values[17]	auto[0]	auto[1]	auto[1]	1885513	1			T1	10		T12	122		T2	8
all_values[17]	auto[1]	auto[0]	auto[1]	29955	1			T1	2		T2	4		T3	17
all_values[17]	auto[1]	auto[1]	auto[1]	28846	1			T1	4		T3	17		T47	1
all_values[18]	auto[0]	auto[0]	auto[0]	2377482	1			T41	137		T42	98		T43	118
all_values[18]	auto[0]	auto[0]	auto[1]	1880462	1			T1	12		T12	140		T2	7
all_values[18]	auto[0]	auto[1]	auto[0]	218706	1			T1	6		T12	9		T2	12
all_values[18]	auto[0]	auto[1]	auto[1]	1891954	1			T1	4		T12	161		T2	22
all_values[18]	auto[1]	auto[0]	auto[1]	29695	1			T1	2		T2	2		T3	10
all_values[18]	auto[1]	auto[1]	auto[1]	29414	1			T1	2		T2	2		T3	19
all_values[19]	auto[0]	auto[0]	auto[0]	2378163	1			T41	137		T42	98		T43	118
all_values[19]	auto[0]	auto[0]	auto[1]	1887316	1			T1	16		T12	142		T2	14
all_values[19]	auto[0]	auto[1]	auto[0]	224091	1			T1	4		T12	33		T2	17
all_values[19]	auto[0]	auto[1]	auto[1]	1878980	1			T12	156		T2	5		T34	152
all_values[19]	auto[1]	auto[0]	auto[1]	29688	1			T1	1		T2	2		T3	18
all_values[19]	auto[1]	auto[1]	auto[1]	29475	1			T1	1		T2	1		T3	12
all_values[20]	auto[0]	auto[0]	auto[0]	2374073	1			T41	137		T42	98		T43	118
all_values[20]	auto[0]	auto[0]	auto[1]	1885596	1			T1	14		T12	138		T2	4
all_values[20]	auto[0]	auto[1]	auto[0]	217977	1			T1	17		T12	55		T2	21
all_values[20]	auto[0]	auto[1]	auto[1]	1891154	1			T12	148		T2	15		T34	141
all_values[20]	auto[1]	auto[0]	auto[1]	29755	1			T1	2		T2	3		T3	17
all_values[20]	auto[1]	auto[1]	auto[1]	29158	1			T2	1		T3	12		T47	1
all_values[21]	auto[0]	auto[0]	auto[0]	2376980	1			T41	137		T42	98		T43	118
all_values[21]	auto[0]	auto[0]	auto[1]	1889928	1			T1	11		T12	141		T2	26
all_values[21]	auto[0]	auto[1]	auto[0]	218575	1			T1	17		T12	64		T2	4
all_values[21]	auto[0]	auto[1]	auto[1]	1883291	1			T1	3		T12	124		T2	3
all_values[21]	auto[1]	auto[0]	auto[1]	29970	1			T1	3		T2	4		T3	13
all_values[21]	auto[1]	auto[1]	auto[1]	28969	1			T1	1		T3	13		T47	2
all_values[22]	auto[0]	auto[0]	auto[0]	2376285	1			T41	137		T42	98		T43	118
all_values[22]	auto[0]	auto[0]	auto[1]	1912153	1			T1	6		T12	108		T2	6
all_values[22]	auto[0]	auto[1]	auto[0]	218569	1			T1	12		T12	47		T2	14
all_values[22]	auto[0]	auto[1]	auto[1]	1861599	1			T1	8		T12	189		T2	3
all_values[22]	auto[1]	auto[0]	auto[1]	30030	1			T1	1		T2	3		T3	8
all_values[22]	auto[1]	auto[1]	auto[1]	29077	1			T1	3		T3	16		T47	2
all_values[23]	auto[0]	auto[0]	auto[0]	2375059	1			T41	137		T42	98		T43	118
all_values[23]	auto[0]	auto[0]	auto[1]	1881069	1			T1	4		T12	144		T2	4
all_values[23]	auto[0]	auto[1]	auto[0]	218928	1			T1	11		T12	32		T2	17
all_values[23]	auto[0]	auto[1]	auto[1]	1893816	1			T1	11		T12	133		T2	6
all_values[23]	auto[1]	auto[0]	auto[1]	29404	1			T1	2		T2	4		T3	15
all_values[23]	auto[1]	auto[1]	auto[1]	29437	1			T1	3		T3	15		T4	18
all_values[24]	auto[0]	auto[0]	auto[0]	2374776	1			T41	137		T42	98		T43	118
all_values[24]	auto[0]	auto[0]	auto[1]	1883869	1			T1	16		T12	125		T2	7
all_values[24]	auto[0]	auto[1]	auto[0]	216833	1			T1	13		T12	40		T2	12
all_values[24]	auto[0]	auto[1]	auto[1]	1893076	1			T1	2		T12	169		T2	17
all_values[24]	auto[1]	auto[0]	auto[1]	29938	1			T1	3		T2	3		T3	15
all_values[24]	auto[1]	auto[1]	auto[1]	29221	1			T1	1		T2	2		T3	15
all_values[25]	auto[0]	auto[0]	auto[0]	2380817	1			T41	137		T42	98		T43	118
all_values[25]	auto[0]	auto[0]	auto[1]	1891853	1			T1	2		T12	141		T2	23
all_values[25]	auto[0]	auto[1]	auto[0]	212595	1			T1	20		T12	53		T2	7
all_values[25]	auto[0]	auto[1]	auto[1]	1883311	1			T12	142		T34	141		T39	947
all_values[25]	auto[1]	auto[0]	auto[1]	29599	1			T1	1		T2	5		T3	14
all_values[25]	auto[1]	auto[1]	auto[1]	29538	1			T1	1		T3	12		T47	2
all_values[26]	auto[0]	auto[0]	auto[0]	2378232	1			T41	137		T42	98		T43	118
all_values[26]	auto[0]	auto[0]	auto[1]	1902530	1			T1	6		T12	100		T2	10
all_values[26]	auto[0]	auto[1]	auto[0]	214910	1			T1	7		T12	25		T2	10
all_values[26]	auto[0]	auto[1]	auto[1]	1873272	1			T1	5		T12	217		T2	18
all_values[26]	auto[1]	auto[0]	auto[1]	29668	1			T1	4		T2	3		T3	15
all_values[26]	auto[1]	auto[1]	auto[1]	29101	1			T1	1		T2	3		T3	17
all_values[27]	auto[0]	auto[0]	auto[0]	2379456	1			T41	137		T42	98		T43	118
all_values[27]	auto[0]	auto[0]	auto[1]	1889011	1			T1	8		T12	185		T34	137
all_values[27]	auto[0]	auto[1]	auto[0]	217554	1			T1	8		T12	23		T2	25
all_values[27]	auto[0]	auto[1]	auto[1]	1882991	1			T1	10		T12	132		T2	14
all_values[27]	auto[1]	auto[0]	auto[1]	29247	1			T1	1		T2	3		T3	19
all_values[27]	auto[1]	auto[1]	auto[1]	29454	1			T1	1		T2	1		T3	8
all_values[28]	auto[0]	auto[0]	auto[0]	2376601	1			T41	137		T42	98		T43	118
all_values[28]	auto[0]	auto[0]	auto[1]	1882503	1			T1	11		T12	137		T2	9
all_values[28]	auto[0]	auto[1]	auto[0]	219009	1			T1	8		T12	38		T2	14
all_values[28]	auto[0]	auto[1]	auto[1]	1890548	1			T1	5		T12	154		T2	12
all_values[28]	auto[1]	auto[0]	auto[1]	29662	1			T1	2		T2	4		T3	15
all_values[28]	auto[1]	auto[1]	auto[1]	29390	1			T1	1		T2	2		T3	18
all_values[29]	auto[0]	auto[0]	auto[0]	2373261	1			T41	137		T42	98		T43	118
all_values[29]	auto[0]	auto[0]	auto[1]	1899316	1			T1	6		T12	154		T2	18
all_values[29]	auto[0]	auto[1]	auto[0]	217684	1			T1	4		T12	3		T2	14
all_values[29]	auto[0]	auto[1]	auto[1]	1878638	1			T1	5		T12	187		T2	5
all_values[29]	auto[1]	auto[0]	auto[1]	29876	1			T1	4		T2	6		T3	21
all_values[29]	auto[1]	auto[1]	auto[1]	28938	1			T1	1		T2	1		T3	10
all_values[30]	auto[0]	auto[0]	auto[0]	2376309	1			T41	137		T42	98		T43	118
all_values[30]	auto[0]	auto[0]	auto[1]	1903273	1			T1	13		T12	165		T2	15
all_values[30]	auto[0]	auto[1]	auto[0]	219875	1			T1	4		T12	15		T2	9
all_values[30]	auto[0]	auto[1]	auto[1]	1869174	1			T1	3		T12	172		T2	12
all_values[30]	auto[1]	auto[0]	auto[1]	29657	1			T1	4		T2	3		T3	12
all_values[30]	auto[1]	auto[1]	auto[1]	29425	1			T2	1		T3	16		T47	2
all_values[31]	auto[0]	auto[0]	auto[0]	2375542	1			T41	137		T42	98		T43	118
all_values[31]	auto[0]	auto[0]	auto[1]	1890785	1			T1	6		T12	125		T2	8
all_values[31]	auto[0]	auto[1]	auto[0]	215334	1			T1	7		T12	39		T2	8
all_values[31]	auto[0]	auto[1]	auto[1]	1887286	1			T1	13		T12	188		T2	14
all_values[31]	auto[1]	auto[0]	auto[1]	29582	1			T1	4		T2	3		T3	8
all_values[31]	auto[1]	auto[1]	auto[1]	29184	1			T1	1		T2	1		T3	18

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal