Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	6377722	1			T41	197		T42	198		T43	218
bins_for_gpio_bits[1]	6377722	1			T41	197		T42	198		T43	218
bins_for_gpio_bits[2]	6377722	1			T41	197		T42	198		T43	218
bins_for_gpio_bits[3]	6377722	1			T41	197		T42	198		T43	218
bins_for_gpio_bits[4]	6377722	1			T41	197		T42	198		T43	218
bins_for_gpio_bits[5]	6377722	1			T41	197		T42	198		T43	218
bins_for_gpio_bits[6]	6377722	1			T41	197		T42	198		T43	218
bins_for_gpio_bits[7]	6377722	1			T41	197		T42	198		T43	218
bins_for_gpio_bits[8]	6377722	1			T41	197		T42	198		T43	218
bins_for_gpio_bits[9]	6377722	1			T41	197		T42	198		T43	218
bins_for_gpio_bits[10]	6377722	1			T41	197		T42	198		T43	218
bins_for_gpio_bits[11]	6377722	1			T41	197		T42	198		T43	218
bins_for_gpio_bits[12]	6377722	1			T41	197		T42	198		T43	218
bins_for_gpio_bits[13]	6377722	1			T41	197		T42	198		T43	218
bins_for_gpio_bits[14]	6377722	1			T41	197		T42	198		T43	218
bins_for_gpio_bits[15]	6377722	1			T41	197		T42	198		T43	218
bins_for_gpio_bits[16]	6377722	1			T41	197		T42	198		T43	218
bins_for_gpio_bits[17]	6377722	1			T41	197		T42	198		T43	218
bins_for_gpio_bits[18]	6377722	1			T41	197		T42	198		T43	218
bins_for_gpio_bits[19]	6377722	1			T41	197		T42	198		T43	218
bins_for_gpio_bits[20]	6377722	1			T41	197		T42	198		T43	218
bins_for_gpio_bits[21]	6377722	1			T41	197		T42	198		T43	218
bins_for_gpio_bits[22]	6377722	1			T41	197		T42	198		T43	218
bins_for_gpio_bits[23]	6377722	1			T41	197		T42	198		T43	218
bins_for_gpio_bits[24]	6377722	1			T41	197		T42	198		T43	218
bins_for_gpio_bits[25]	6377722	1			T41	197		T42	198		T43	218
bins_for_gpio_bits[26]	6377722	1			T41	197		T42	198		T43	218
bins_for_gpio_bits[27]	6377722	1			T41	197		T42	198		T43	218
bins_for_gpio_bits[28]	6377722	1			T41	197		T42	198		T43	218
bins_for_gpio_bits[29]	6377722	1			T41	197		T42	198		T43	218
bins_for_gpio_bits[30]	6377722	1			T41	197		T42	198		T43	218
bins_for_gpio_bits[31]	6377722	1			T41	197		T42	198		T43	218

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

109906777

1

T41

4087

T42

4894

T43

5563

auto[1]

94180327

1

T41

2217

T42

1442

T43

1413

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

169765008

1

T41

4452

T42

5125

T43

5172

auto[1]

34322096

1

T41

1852

T42

1211

T43

1804

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

159760629

1

T41

4325

T42

3147

T43

3231

auto[1]

44326475

1

T41

1979

T42

3189

T43

3745

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	2350465	1			T41	61		T42	92		T43	81
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	2103285	1			T41	40		T42	15		T43	7
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	540276	1			T41	12		T42	30		T43	25
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	545775	1			T41	48		T42	34		T43	70
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	305303	1			T42	10		T43	5		T44	60
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	532618	1			T41	36		T42	17		T43	30
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	2351059	1			T41	56		T42	72		T43	92
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	2103163	1			T41	39		T42	11		T43	7
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	538336	1			T41	26		T42	26		T43	10
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	545295	1			T41	34		T42	59		T43	89
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	306567	1			T42	11		T43	8		T44	44
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	533302	1			T41	42		T42	19		T43	12
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	2345907	1			T41	72		T42	50		T43	27
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	2103717	1			T41	38		T42	8		T43	3
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	539867	1			T41	20		T42	10		T43	22
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	548360	1			T41	27		T42	98		T43	122
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	305277	1			T42	13		T43	12		T44	52
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	534594	1			T41	40		T42	19		T43	32
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	2360691	1			T41	71		T42	61		T43	51
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	2092888	1			T41	39		T42	12		T43	5
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	538913	1			T41	24		T42	6		T43	10
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	546129	1			T41	27		T42	84		T43	105
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	305541	1			T42	16		T43	7		T44	90
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	533560	1			T41	36		T42	19		T43	40
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	2353496	1			T41	71		T42	35		T43	69
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	2103931	1			T41	33		T43	5		T44	51
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	543523	1			T41	26		T42	5		T43	20
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	541358	1			T41	32		T42	100		T43	81
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	303490	1			T42	26		T43	10		T44	76
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	531924	1			T41	35		T42	32		T43	33
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	2343271	1			T41	63		T42	69		T43	65
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	2113034	1			T41	47		T42	10		T43	5
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	535487	1			T41	35		T42	14		T43	22
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	547026	1			T41	26		T42	56		T43	75
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	303221	1			T42	14		T43	8		T44	3
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	535683	1			T41	26		T42	35		T43	43
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	2356143	1			T41	65		T42	79		T43	76
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	2092428	1			T41	41		T42	16		T43	8
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	539206	1			T41	28		T42	38		T43	32
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	545840	1			T41	31		T42	37		T43	72
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	307061	1			T42	9		T43	6		T44	78
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	537044	1			T41	32		T42	19		T43	24
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	2344139	1			T41	63		T42	62		T43	74
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	2110842	1			T41	43		T42	3		T43	5
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	542229	1			T41	31		T42	30		T43	26
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	541402	1			T41	22		T42	69		T43	78
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	302667	1			T42	14		T43	4		T44	39
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	536443	1			T41	38		T42	20		T43	31
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	2348891	1			T41	82		T42	74		T43	77
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	2102089	1			T41	38		T42	17		T43	7
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	539763	1			T41	26		T42	27		T43	20
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	544535	1			T41	25		T42	59		T43	70
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	305831	1			T42	4		T43	4		T44	53
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	536613	1			T41	26		T42	17		T43	40
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	2348323	1			T41	65		T42	74		T43	93
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	2107915	1			T41	39		T42	22		T43	9
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	540693	1			T41	45		T42	10		T43	31
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	544535	1			T41	24		T42	60		T43	68
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	302904	1			T42	4		T43	3		T44	85
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	533352	1			T41	24		T42	28		T43	14
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	2354201	1			T41	86		T42	62		T43	60
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	2097850	1			T41	36		T42	13		T43	7
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	539236	1			T41	24		T42	20		T43	24
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	545737	1			T41	30		T42	76		T43	86
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	305123	1			T42	9		T43	9		T44	53
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	535575	1			T41	21		T42	18		T43	32
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	2341518	1			T41	75		T42	67		T43	45
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	2111042	1			T41	34		T42	9		T43	5
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	538351	1			T41	24		T42	15		T43	22
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	547825	1			T41	32		T42	63		T43	80
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	304551	1			T42	19		T43	9		T44	34
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	534435	1			T41	32		T42	25		T43	57
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	2350725	1			T41	79		T42	99		T43	75
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	2100176	1			T41	35		T42	30		T43	10
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	540030	1			T41	32		T42	25		T43	20
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	546507	1			T41	26		T42	33		T43	82
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	305458	1			T42	1		T43	8		T1	7
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	534826	1			T41	25		T42	10		T43	23
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	2341418	1			T41	61		T42	64		T43	78
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	2103598	1			T41	38		T42	5		T43	10
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	536918	1			T41	30		T42	6		T43	42
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	549522	1			T41	38		T42	86		T43	58
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	306156	1			T42	19		T43	6		T44	45
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	540110	1			T41	30		T42	18		T43	24
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	2351998	1			T41	73		T42	31		T43	38
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	2099548	1			T41	43		T42	1		T43	3
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	541519	1			T41	37		T43	32		T44	6
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	542732	1			T41	20		T42	119		T43	84
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	306583	1			T42	22		T43	8		T44	59
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	535342	1			T41	24		T42	25		T43	53
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	2350980	1			T41	68		T42	94		T43	42
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	2103505	1			T41	44		T42	25		T43	5
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	541432	1			T41	29		T42	31		T43	29
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	544185	1			T41	36		T42	38		T43	104
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	305494	1			T42	2		T43	8		T44	40
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	532126	1			T41	20		T42	8		T43	30
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	2353606	1			T41	68		T42	67		T43	77
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	2103138	1			T41	39		T42	8		T43	6
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	537694	1			T41	26		T42	30		T43	42
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	546818	1			T41	22		T42	55		T43	67
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	305112	1			T42	23		T43	5		T44	36
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	531354	1			T41	42		T42	15		T43	21
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	2351131	1			T41	93		T42	69		T43	53
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	2102873	1			T41	39		T42	14		T43	5
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	540317	1			T41	30		T42	26		T43	28
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	546583	1			T41	16		T42	65		T43	89
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	303914	1			T42	13		T43	10		T44	32
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	532904	1			T41	19		T42	11		T43	33
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	2347965	1			T41	81		T42	32		T43	111
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	2104656	1			T41	37		T42	9		T43	6
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	536407	1			T41	31		T43	6		T44	22
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	548495	1			T41	30		T42	108		T43	60
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	307064	1			T42	16		T43	4		T44	37
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	533135	1			T41	18		T42	33		T43	31
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	2350408	1			T41	57		T42	59		T43	96
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	2102384	1			T41	37		T42	17		T43	7
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	538579	1			T41	24		T42	19		T43	28
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	546086	1			T41	42		T42	79		T43	62
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	305990	1			T42	12		T43	5		T44	45
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	534275	1			T41	37		T42	12		T43	20
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	2355539	1			T41	70		T42	91		T43	74
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	2098659	1			T41	40		T42	32		T43	9
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	538844	1			T41	16		T42	34		T43	28
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	545752	1			T41	39		T42	32		T43	66
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	308108	1			T42	3		T43	8		T44	59
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	530820	1			T41	32		T42	6		T43	33
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	2348386	1			T41	51		T42	70		T43	82
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	2105493	1			T41	42		T42	9		T43	10
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	540529	1			T41	28		T42	11		T43	22
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	543090	1			T41	36		T42	55		T43	72
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	306120	1			T42	15		T43	8		T44	33
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	534104	1			T41	40		T42	38		T43	24
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	2352386	1			T41	65		T42	58		T43	42
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	2099218	1			T41	31		T42	9		T43	8
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	538458	1			T41	22		T42	9		T43	34
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	546896	1			T41	36		T42	91		T43	93
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	304819	1			T42	16		T43	8		T44	44
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	535945	1			T41	43		T42	15		T43	33
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	2350057	1			T41	71		T42	73		T43	75
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	2106572	1			T41	27		T42	12		T43	1
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	537180	1			T41	20		T42	21		T43	30
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	547884	1			T41	39		T42	61		T43	83
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	303490	1			T42	9		T43	7		T44	65
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	532539	1			T41	40		T42	22		T43	22
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	2354659	1			T41	75		T42	67		T43	60
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	2104908	1			T41	30		T42	9		T43	5
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	537992	1			T41	24		T42	16		T43	21
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	542467	1			T41	32		T42	73		T43	96
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	306572	1			T42	25		T43	8		T44	52
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	531124	1			T41	36		T42	8		T43	28
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	2348812	1			T41	86		T42	61		T43	84
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	2107199	1			T41	37		T42	17		T43	8
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	537961	1			T41	38		T42	23		T43	39
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	547866	1			T41	22		T42	61		T43	65
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	306467	1			T42	11		T43	4		T44	77
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	529417	1			T41	14		T42	25		T43	18
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	2354865	1			T41	58		T42	101		T43	60
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	2103700	1			T41	50		T42	13		T43	12
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	538756	1			T41	30		T42	12		T43	42
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	545887	1			T41	24		T42	53		T43	66
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	304080	1			T42	4		T43	3		T44	39
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	530434	1			T41	35		T42	15		T43	35
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	2341269	1			T41	75		T42	85		T43	54
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	2110101	1			T41	35		T42	12		T43	9
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	537671	1			T41	24		T42	20		T43	22
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	549057	1			T41	31		T42	51		T43	84
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	304714	1			T42	15		T43	5		T44	65
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	534910	1			T41	32		T42	15		T43	44
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	2347444	1			T41	71		T42	63		T43	58
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	2109858	1			T41	39		T42	7		T43	7
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	539745	1			T41	28		T42	11		T43	22
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	547179	1			T41	30		T42	80		T43	75
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	305063	1			T42	27		T43	8		T44	52
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	528433	1			T41	29		T42	10		T43	48
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	2351092	1			T41	74		T42	65		T43	98
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	2103819	1			T41	38		T42	13		T43	4
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	536712	1			T41	26		T42	17		T43	40
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	544846	1			T41	29		T42	55		T43	51
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	307009	1			T42	19		T43	4		T44	65
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	534244	1			T41	30		T42	29		T43	21
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	2339102	1			T41	66		T42	78		T43	61
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	2111931	1			T41	42		T42	20		T43	9
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	535532	1			T41	17		T42	48		T43	18
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	550471	1			T41	44		T42	36		T43	91
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	306552	1			T42	2		T43	12		T44	27
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	534134	1			T41	28		T42	14		T43	27
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	2348652	1			T41	78		T42	28		T43	69
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	2104380	1			T41	30		T42	1		T43	5
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	535975	1			T41	22		T42	6		T43	13
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	547908	1			T41	32		T42	120		T43	100
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	308161	1			T42	25		T43	5		T44	63
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	532646	1			T41	35		T42	18		T43	26

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal