Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	6377722	1			T41	197		T42	198		T43	218
bins_for_gpio_bits[1]	6377722	1			T41	197		T42	198		T43	218
bins_for_gpio_bits[2]	6377722	1			T41	197		T42	198		T43	218
bins_for_gpio_bits[3]	6377722	1			T41	197		T42	198		T43	218
bins_for_gpio_bits[4]	6377722	1			T41	197		T42	198		T43	218
bins_for_gpio_bits[5]	6377722	1			T41	197		T42	198		T43	218
bins_for_gpio_bits[6]	6377722	1			T41	197		T42	198		T43	218
bins_for_gpio_bits[7]	6377722	1			T41	197		T42	198		T43	218
bins_for_gpio_bits[8]	6377722	1			T41	197		T42	198		T43	218
bins_for_gpio_bits[9]	6377722	1			T41	197		T42	198		T43	218
bins_for_gpio_bits[10]	6377722	1			T41	197		T42	198		T43	218
bins_for_gpio_bits[11]	6377722	1			T41	197		T42	198		T43	218
bins_for_gpio_bits[12]	6377722	1			T41	197		T42	198		T43	218
bins_for_gpio_bits[13]	6377722	1			T41	197		T42	198		T43	218
bins_for_gpio_bits[14]	6377722	1			T41	197		T42	198		T43	218
bins_for_gpio_bits[15]	6377722	1			T41	197		T42	198		T43	218
bins_for_gpio_bits[16]	6377722	1			T41	197		T42	198		T43	218
bins_for_gpio_bits[17]	6377722	1			T41	197		T42	198		T43	218
bins_for_gpio_bits[18]	6377722	1			T41	197		T42	198		T43	218
bins_for_gpio_bits[19]	6377722	1			T41	197		T42	198		T43	218
bins_for_gpio_bits[20]	6377722	1			T41	197		T42	198		T43	218
bins_for_gpio_bits[21]	6377722	1			T41	197		T42	198		T43	218
bins_for_gpio_bits[22]	6377722	1			T41	197		T42	198		T43	218
bins_for_gpio_bits[23]	6377722	1			T41	197		T42	198		T43	218
bins_for_gpio_bits[24]	6377722	1			T41	197		T42	198		T43	218
bins_for_gpio_bits[25]	6377722	1			T41	197		T42	198		T43	218
bins_for_gpio_bits[26]	6377722	1			T41	197		T42	198		T43	218
bins_for_gpio_bits[27]	6377722	1			T41	197		T42	198		T43	218
bins_for_gpio_bits[28]	6377722	1			T41	197		T42	198		T43	218
bins_for_gpio_bits[29]	6377722	1			T41	197		T42	198		T43	218
bins_for_gpio_bits[30]	6377722	1			T41	197		T42	198		T43	218
bins_for_gpio_bits[31]	6377722	1			T41	197		T42	198		T43	218

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

109906777

1

T41

4087

T42

4894

T43

5563

auto[1]

94180327

1

T41

2217

T42

1442

T43

1413

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

109898678

1

T41

4078

T42

4882

T43

5563

auto[1]

94188426

1

T41

2226

T42

1454

T43

1413

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	3340006	1			T41	114		T42	152		T43	169
bins_for_gpio_bits[0]	auto[0]	auto[1]	96260	1			T41	7		T42	4		T43	7
bins_for_gpio_bits[0]	auto[1]	auto[0]	96510	1			T41	7		T42	4		T43	7
bins_for_gpio_bits[0]	auto[1]	auto[1]	2844946	1			T41	69		T42	38		T43	35
bins_for_gpio_bits[1]	auto[0]	auto[0]	3337923	1			T41	110		T42	152		T43	186
bins_for_gpio_bits[1]	auto[0]	auto[1]	96506	1			T41	6		T42	4		T43	5
bins_for_gpio_bits[1]	auto[1]	auto[0]	96767	1			T41	6		T42	5		T43	5
bins_for_gpio_bits[1]	auto[1]	auto[1]	2846526	1			T41	75		T42	37		T43	22
bins_for_gpio_bits[2]	auto[0]	auto[0]	3337451	1			T41	110		T42	153		T43	164
bins_for_gpio_bits[2]	auto[0]	auto[1]	96471	1			T41	9		T42	4		T43	7
bins_for_gpio_bits[2]	auto[1]	auto[0]	96683	1			T41	9		T42	5		T43	7
bins_for_gpio_bits[2]	auto[1]	auto[1]	2847117	1			T41	69		T42	36		T43	40
bins_for_gpio_bits[3]	auto[0]	auto[0]	3348792	1			T41	115		T42	147		T43	159
bins_for_gpio_bits[3]	auto[0]	auto[1]	96660	1			T41	7		T42	3		T43	7
bins_for_gpio_bits[3]	auto[1]	auto[0]	96941	1			T41	7		T42	4		T43	7
bins_for_gpio_bits[3]	auto[1]	auto[1]	2835329	1			T41	68		T42	44		T43	45
bins_for_gpio_bits[4]	auto[0]	auto[0]	3341776	1			T41	123		T42	137		T43	166
bins_for_gpio_bits[4]	auto[0]	auto[1]	96356	1			T41	5		T42	3		T43	4
bins_for_gpio_bits[4]	auto[1]	auto[0]	96601	1			T41	6		T42	3		T43	4
bins_for_gpio_bits[4]	auto[1]	auto[1]	2842989	1			T41	63		T42	55		T43	44
bins_for_gpio_bits[5]	auto[0]	auto[0]	3328825	1			T41	117		T42	134		T43	156
bins_for_gpio_bits[5]	auto[0]	auto[1]	96683	1			T41	7		T42	5		T43	6
bins_for_gpio_bits[5]	auto[1]	auto[0]	96959	1			T41	7		T42	5		T43	6
bins_for_gpio_bits[5]	auto[1]	auto[1]	2855255	1			T41	66		T42	54		T43	50
bins_for_gpio_bits[6]	auto[0]	auto[0]	3344413	1			T41	114		T42	149		T43	175
bins_for_gpio_bits[6]	auto[0]	auto[1]	96542	1			T41	10		T42	4		T43	5
bins_for_gpio_bits[6]	auto[1]	auto[0]	96776	1			T41	10		T42	5		T43	5
bins_for_gpio_bits[6]	auto[1]	auto[1]	2839991	1			T41	63		T42	40		T43	33
bins_for_gpio_bits[7]	auto[0]	auto[0]	3330862	1			T41	110		T42	156		T43	172
bins_for_gpio_bits[7]	auto[0]	auto[1]	96658	1			T41	6		T42	5		T43	6
bins_for_gpio_bits[7]	auto[1]	auto[0]	96908	1			T41	6		T42	5		T43	6
bins_for_gpio_bits[7]	auto[1]	auto[1]	2853294	1			T41	75		T42	32		T43	34
bins_for_gpio_bits[8]	auto[0]	auto[0]	3336259	1			T41	128		T42	158		T43	160
bins_for_gpio_bits[8]	auto[0]	auto[1]	96686	1			T41	5		T42	2		T43	7
bins_for_gpio_bits[8]	auto[1]	auto[0]	96930	1			T41	5		T42	2		T43	7
bins_for_gpio_bits[8]	auto[1]	auto[1]	2847847	1			T41	59		T42	36		T43	44
bins_for_gpio_bits[9]	auto[0]	auto[0]	3336784	1			T41	126		T42	139		T43	188
bins_for_gpio_bits[9]	auto[0]	auto[1]	96509	1			T41	8		T42	5		T43	4
bins_for_gpio_bits[9]	auto[1]	auto[0]	96767	1			T41	8		T42	5		T43	4
bins_for_gpio_bits[9]	auto[1]	auto[1]	2847662	1			T41	55		T42	49		T43	22
bins_for_gpio_bits[10]	auto[0]	auto[0]	3342285	1			T41	135		T42	153		T43	165
bins_for_gpio_bits[10]	auto[0]	auto[1]	96640	1			T41	4		T42	4		T43	5
bins_for_gpio_bits[10]	auto[1]	auto[0]	96889	1			T41	5		T42	5		T43	5
bins_for_gpio_bits[10]	auto[1]	auto[1]	2841908	1			T41	53		T42	36		T43	43
bins_for_gpio_bits[11]	auto[0]	auto[0]	3330902	1			T41	122		T42	140		T43	134
bins_for_gpio_bits[11]	auto[0]	auto[1]	96499	1			T41	9		T42	4		T43	13
bins_for_gpio_bits[11]	auto[1]	auto[0]	96792	1			T41	9		T42	5		T43	13
bins_for_gpio_bits[11]	auto[1]	auto[1]	2853529	1			T41	57		T42	49		T43	58
bins_for_gpio_bits[12]	auto[0]	auto[0]	3340385	1			T41	131		T42	155		T43	172
bins_for_gpio_bits[12]	auto[0]	auto[1]	96594	1			T41	5		T42	2		T43	5
bins_for_gpio_bits[12]	auto[1]	auto[0]	96877	1			T41	6		T42	2		T43	5
bins_for_gpio_bits[12]	auto[1]	auto[1]	2843866	1			T41	55		T42	39		T43	36
bins_for_gpio_bits[13]	auto[0]	auto[0]	3330953	1			T41	119		T42	153		T43	173
bins_for_gpio_bits[13]	auto[0]	auto[1]	96635	1			T41	10		T42	3		T43	5
bins_for_gpio_bits[13]	auto[1]	auto[0]	96905	1			T41	10		T42	3		T43	5
bins_for_gpio_bits[13]	auto[1]	auto[1]	2853229	1			T41	58		T42	39		T43	35
bins_for_gpio_bits[14]	auto[0]	auto[0]	3339332	1			T41	121		T42	145		T43	143
bins_for_gpio_bits[14]	auto[0]	auto[1]	96694	1			T41	9		T42	4		T43	11
bins_for_gpio_bits[14]	auto[1]	auto[0]	96917	1			T41	9		T42	5		T43	11
bins_for_gpio_bits[14]	auto[1]	auto[1]	2844779	1			T41	58		T42	44		T43	53
bins_for_gpio_bits[15]	auto[0]	auto[0]	3339930	1			T41	125		T42	159		T43	170
bins_for_gpio_bits[15]	auto[0]	auto[1]	96434	1			T41	8		T42	4		T43	5
bins_for_gpio_bits[15]	auto[1]	auto[0]	96667	1			T41	8		T42	4		T43	5
bins_for_gpio_bits[15]	auto[1]	auto[1]	2844691	1			T41	56		T42	31		T43	38
bins_for_gpio_bits[16]	auto[0]	auto[0]	3341074	1			T41	108		T42	149		T43	182
bins_for_gpio_bits[16]	auto[0]	auto[1]	96786	1			T41	8		T42	3		T43	4
bins_for_gpio_bits[16]	auto[1]	auto[0]	97044	1			T41	8		T42	3		T43	4
bins_for_gpio_bits[16]	auto[1]	auto[1]	2842818	1			T41	73		T42	43		T43	28
bins_for_gpio_bits[17]	auto[0]	auto[0]	3340985	1			T41	133		T42	158		T43	164
bins_for_gpio_bits[17]	auto[0]	auto[1]	96766	1			T41	5		T42	2		T43	6
bins_for_gpio_bits[17]	auto[1]	auto[0]	97046	1			T41	6		T42	2		T43	6
bins_for_gpio_bits[17]	auto[1]	auto[1]	2842925	1			T41	53		T42	36		T43	42
bins_for_gpio_bits[18]	auto[0]	auto[0]	3335782	1			T41	136		T42	134		T43	172
bins_for_gpio_bits[18]	auto[0]	auto[1]	96831	1			T41	6		T42	6		T43	5
bins_for_gpio_bits[18]	auto[1]	auto[0]	97085	1			T41	6		T42	6		T43	5
bins_for_gpio_bits[18]	auto[1]	auto[1]	2848024	1			T41	49		T42	52		T43	36
bins_for_gpio_bits[19]	auto[0]	auto[0]	3338071	1			T41	114		T42	153		T43	182
bins_for_gpio_bits[19]	auto[0]	auto[1]	96738	1			T41	8		T42	4		T43	4
bins_for_gpio_bits[19]	auto[1]	auto[0]	97002	1			T41	9		T42	4		T43	4
bins_for_gpio_bits[19]	auto[1]	auto[1]	2845911	1			T41	66		T42	37		T43	28
bins_for_gpio_bits[20]	auto[0]	auto[0]	3343326	1			T41	119		T42	155		T43	161
bins_for_gpio_bits[20]	auto[0]	auto[1]	96535	1			T41	6		T42	2		T43	7
bins_for_gpio_bits[20]	auto[1]	auto[0]	96809	1			T41	6		T42	2		T43	7
bins_for_gpio_bits[20]	auto[1]	auto[1]	2841052	1			T41	66		T42	39		T43	43
bins_for_gpio_bits[21]	auto[0]	auto[0]	3334872	1			T41	105		T42	130		T43	172
bins_for_gpio_bits[21]	auto[0]	auto[1]	96875	1			T41	10		T42	6		T43	4
bins_for_gpio_bits[21]	auto[1]	auto[0]	97133	1			T41	10		T42	6		T43	4
bins_for_gpio_bits[21]	auto[1]	auto[1]	2848842	1			T41	72		T42	56		T43	38
bins_for_gpio_bits[22]	auto[0]	auto[0]	3340709	1			T41	113		T42	155		T43	161
bins_for_gpio_bits[22]	auto[0]	auto[1]	96795	1			T41	9		T42	3		T43	8
bins_for_gpio_bits[22]	auto[1]	auto[0]	97031	1			T41	10		T42	3		T43	8
bins_for_gpio_bits[22]	auto[1]	auto[1]	2843187	1			T41	65		T42	37		T43	41
bins_for_gpio_bits[23]	auto[0]	auto[0]	3338558	1			T41	120		T42	150		T43	183
bins_for_gpio_bits[23]	auto[0]	auto[1]	96327	1			T41	10		T42	5		T43	5
bins_for_gpio_bits[23]	auto[1]	auto[0]	96563	1			T41	10		T42	5		T43	5
bins_for_gpio_bits[23]	auto[1]	auto[1]	2846274	1			T41	57		T42	38		T43	25
bins_for_gpio_bits[24]	auto[0]	auto[0]	3338648	1			T41	122		T42	153		T43	169
bins_for_gpio_bits[24]	auto[0]	auto[1]	96195	1			T41	9		T42	3		T43	8
bins_for_gpio_bits[24]	auto[1]	auto[0]	96470	1			T41	9		T42	3		T43	8
bins_for_gpio_bits[24]	auto[1]	auto[1]	2846409	1			T41	57		T42	39		T43	33
bins_for_gpio_bits[25]	auto[0]	auto[0]	3337833	1			T41	140		T42	140		T43	182
bins_for_gpio_bits[25]	auto[0]	auto[1]	96584	1			T41	6		T42	4		T43	6
bins_for_gpio_bits[25]	auto[1]	auto[0]	96806	1			T41	6		T42	5		T43	6
bins_for_gpio_bits[25]	auto[1]	auto[1]	2846499	1			T41	45		T42	49		T43	24
bins_for_gpio_bits[26]	auto[0]	auto[0]	3342743	1			T41	102		T42	162		T43	162
bins_for_gpio_bits[26]	auto[0]	auto[1]	96536	1			T41	9		T42	3		T43	6
bins_for_gpio_bits[26]	auto[1]	auto[0]	96765	1			T41	10		T42	4		T43	6
bins_for_gpio_bits[26]	auto[1]	auto[1]	2841678	1			T41	76		T42	29		T43	44
bins_for_gpio_bits[27]	auto[0]	auto[0]	3331132	1			T41	121		T42	153		T43	152
bins_for_gpio_bits[27]	auto[0]	auto[1]	96591	1			T41	9		T42	2		T43	8
bins_for_gpio_bits[27]	auto[1]	auto[0]	96865	1			T41	9		T42	3		T43	8
bins_for_gpio_bits[27]	auto[1]	auto[1]	2853134	1			T41	58		T42	40		T43	50
bins_for_gpio_bits[28]	auto[0]	auto[0]	3337805	1			T41	120		T42	151		T43	148
bins_for_gpio_bits[28]	auto[0]	auto[1]	96337	1			T41	8		T42	3		T43	7
bins_for_gpio_bits[28]	auto[1]	auto[0]	96563	1			T41	9		T42	3		T43	7
bins_for_gpio_bits[28]	auto[1]	auto[1]	2847017	1			T41	60		T42	41		T43	56
bins_for_gpio_bits[29]	auto[0]	auto[0]	3336142	1			T41	121		T42	131		T43	184
bins_for_gpio_bits[29]	auto[0]	auto[1]	96240	1			T41	8		T42	5		T43	5
bins_for_gpio_bits[29]	auto[1]	auto[0]	96508	1			T41	8		T42	6		T43	5
bins_for_gpio_bits[29]	auto[1]	auto[1]	2848832	1			T41	60		T42	56		T43	24
bins_for_gpio_bits[30]	auto[0]	auto[0]	3328375	1			T41	118		T42	158		T43	165
bins_for_gpio_bits[30]	auto[0]	auto[1]	96495	1			T41	9		T42	3		T43	5
bins_for_gpio_bits[30]	auto[1]	auto[0]	96730	1			T41	9		T42	4		T43	5
bins_for_gpio_bits[30]	auto[1]	auto[1]	2856122	1			T41	61		T42	33		T43	43
bins_for_gpio_bits[31]	auto[0]	auto[0]	3335868	1			T41	125		T42	150		T43	176
bins_for_gpio_bits[31]	auto[0]	auto[1]	96419	1			T41	6		T42	4		T43	6
bins_for_gpio_bits[31]	auto[1]	auto[0]	96667	1			T41	7		T42	4		T43	6
bins_for_gpio_bits[31]	auto[1]	auto[1]	2848768	1			T41	59		T42	40		T43	30