Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4289217 |
1 |
|
|
T41 |
137 |
|
T42 |
98 |
|
T43 |
118 |
| auto[1] |
2138496 |
1 |
|
|
T1 |
27 |
|
T12 |
169 |
|
T2 |
19 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6160011 |
1 |
|
|
T41 |
137 |
|
T42 |
98 |
|
T43 |
118 |
| auto[1] |
267702 |
1 |
|
|
T12 |
15 |
|
T34 |
15 |
|
T39 |
167 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4305558 |
1 |
|
|
T41 |
137 |
|
T42 |
98 |
|
T43 |
118 |
| auto[1] |
2122155 |
1 |
|
|
T12 |
247 |
|
T2 |
5 |
|
T34 |
200 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
925967 |
1 |
|
|
T12 |
136 |
|
T2 |
1 |
|
T34 |
93 |
| auto[1] |
auto[0] |
auto[1] |
133347 |
1 |
|
|
T12 |
9 |
|
T34 |
9 |
|
T39 |
101 |
| auto[1] |
auto[1] |
auto[0] |
928486 |
1 |
|
|
T12 |
96 |
|
T2 |
4 |
|
T34 |
92 |
| auto[1] |
auto[1] |
auto[1] |
134355 |
1 |
|
|
T12 |
6 |
|
T34 |
6 |
|
T39 |
66 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |