Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4313916 |
1 |
|
|
T41 |
137 |
|
T42 |
98 |
|
T43 |
118 |
| auto[1] |
2113797 |
1 |
|
|
T1 |
27 |
|
T12 |
200 |
|
T2 |
10 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6160574 |
1 |
|
|
T41 |
137 |
|
T42 |
98 |
|
T43 |
118 |
| auto[1] |
267139 |
1 |
|
|
T12 |
15 |
|
T2 |
1 |
|
T34 |
17 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4300886 |
1 |
|
|
T41 |
137 |
|
T42 |
98 |
|
T43 |
118 |
| auto[1] |
2126827 |
1 |
|
|
T1 |
10 |
|
T12 |
234 |
|
T2 |
15 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
946751 |
1 |
|
|
T1 |
2 |
|
T12 |
106 |
|
T2 |
14 |
| auto[1] |
auto[0] |
auto[1] |
136340 |
1 |
|
|
T12 |
8 |
|
T2 |
1 |
|
T34 |
12 |
| auto[1] |
auto[1] |
auto[0] |
912937 |
1 |
|
|
T1 |
8 |
|
T12 |
113 |
|
T34 |
80 |
| auto[1] |
auto[1] |
auto[1] |
130799 |
1 |
|
|
T12 |
7 |
|
T34 |
5 |
|
T39 |
60 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |