Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4290705 |
1 |
|
|
T41 |
137 |
|
T42 |
98 |
|
T43 |
118 |
| auto[1] |
2137008 |
1 |
|
|
T1 |
30 |
|
T12 |
205 |
|
T2 |
19 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5444243 |
1 |
|
|
T41 |
137 |
|
T42 |
98 |
|
T43 |
118 |
| auto[1] |
983470 |
1 |
|
|
T1 |
2 |
|
T12 |
111 |
|
T2 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4297032 |
1 |
|
|
T41 |
137 |
|
T42 |
98 |
|
T43 |
118 |
| auto[1] |
2130681 |
1 |
|
|
T1 |
4 |
|
T12 |
215 |
|
T2 |
10 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
576050 |
1 |
|
|
T1 |
2 |
|
T12 |
37 |
|
T34 |
45 |
| auto[1] |
auto[0] |
auto[1] |
493907 |
1 |
|
|
T12 |
39 |
|
T2 |
3 |
|
T34 |
34 |
| auto[1] |
auto[1] |
auto[0] |
571161 |
1 |
|
|
T12 |
67 |
|
T2 |
7 |
|
T34 |
55 |
| auto[1] |
auto[1] |
auto[1] |
489563 |
1 |
|
|
T1 |
2 |
|
T12 |
72 |
|
T34 |
37 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |