Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4318468 |
1 |
|
|
T41 |
137 |
|
T42 |
98 |
|
T43 |
118 |
| auto[1] |
2109245 |
1 |
|
|
T1 |
23 |
|
T12 |
236 |
|
T2 |
17 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5451293 |
1 |
|
|
T41 |
137 |
|
T42 |
98 |
|
T43 |
118 |
| auto[1] |
976420 |
1 |
|
|
T1 |
4 |
|
T12 |
123 |
|
T34 |
86 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4311672 |
1 |
|
|
T41 |
137 |
|
T42 |
98 |
|
T43 |
118 |
| auto[1] |
2116041 |
1 |
|
|
T1 |
6 |
|
T12 |
187 |
|
T34 |
135 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
576982 |
1 |
|
|
T1 |
2 |
|
T12 |
17 |
|
T34 |
13 |
| auto[1] |
auto[0] |
auto[1] |
495327 |
1 |
|
|
T1 |
4 |
|
T12 |
47 |
|
T34 |
48 |
| auto[1] |
auto[1] |
auto[0] |
562639 |
1 |
|
|
T12 |
47 |
|
T34 |
36 |
|
T39 |
127 |
| auto[1] |
auto[1] |
auto[1] |
481093 |
1 |
|
|
T12 |
76 |
|
T34 |
38 |
|
T39 |
137 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |