Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4297714 |
1 |
|
|
T41 |
137 |
|
T42 |
98 |
|
T43 |
118 |
| auto[1] |
2129999 |
1 |
|
|
T1 |
19 |
|
T12 |
155 |
|
T2 |
40 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6160588 |
1 |
|
|
T41 |
137 |
|
T42 |
98 |
|
T43 |
118 |
| auto[1] |
267125 |
1 |
|
|
T12 |
11 |
|
T34 |
11 |
|
T39 |
134 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4300614 |
1 |
|
|
T41 |
137 |
|
T42 |
98 |
|
T43 |
118 |
| auto[1] |
2127099 |
1 |
|
|
T1 |
14 |
|
T12 |
176 |
|
T2 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
930004 |
1 |
|
|
T1 |
8 |
|
T12 |
110 |
|
T2 |
3 |
| auto[1] |
auto[0] |
auto[1] |
133929 |
1 |
|
|
T12 |
8 |
|
T34 |
4 |
|
T39 |
54 |
| auto[1] |
auto[1] |
auto[0] |
929970 |
1 |
|
|
T1 |
6 |
|
T12 |
55 |
|
T34 |
97 |
| auto[1] |
auto[1] |
auto[1] |
133196 |
1 |
|
|
T12 |
3 |
|
T34 |
7 |
|
T39 |
80 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |