Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	1741774	1			T25	1		T26	1		T27	1
all_pins[1]	1741774	1			T25	1		T26	1		T27	1
all_pins[2]	1741774	1			T25	1		T26	1		T27	1
all_pins[3]	1741774	1			T25	1		T26	1		T27	1
all_pins[4]	1741774	1			T25	1		T26	1		T27	1
all_pins[5]	1741774	1			T25	1		T26	1		T27	1
all_pins[6]	1741774	1			T25	1		T26	1		T27	1
all_pins[7]	1741774	1			T25	1		T26	1		T27	1
all_pins[8]	1741774	1			T25	1		T26	1		T27	1
all_pins[9]	1741774	1			T25	1		T26	1		T27	1
all_pins[10]	1741774	1			T25	1		T26	1		T27	1
all_pins[11]	1741774	1			T25	1		T26	1		T27	1
all_pins[12]	1741774	1			T25	1		T26	1		T27	1
all_pins[13]	1741774	1			T25	1		T26	1		T27	1
all_pins[14]	1741774	1			T25	1		T26	1		T27	1
all_pins[15]	1741774	1			T25	1		T26	1		T27	1
all_pins[16]	1741774	1			T25	1		T26	1		T27	1
all_pins[17]	1741774	1			T25	1		T26	1		T27	1
all_pins[18]	1741774	1			T25	1		T26	1		T27	1
all_pins[19]	1741774	1			T25	1		T26	1		T27	1
all_pins[20]	1741774	1			T25	1		T26	1		T27	1
all_pins[21]	1741774	1			T25	1		T26	1		T27	1
all_pins[22]	1741774	1			T25	1		T26	1		T27	1
all_pins[23]	1741774	1			T25	1		T26	1		T27	1
all_pins[24]	1741774	1			T25	1		T26	1		T27	1
all_pins[25]	1741774	1			T25	1		T26	1		T27	1
all_pins[26]	1741774	1			T25	1		T26	1		T27	1
all_pins[27]	1741774	1			T25	1		T26	1		T27	1
all_pins[28]	1741774	1			T25	1		T26	1		T27	1
all_pins[29]	1741774	1			T25	1		T26	1		T27	1
all_pins[30]	1741774	1			T25	1		T26	1		T27	1
all_pins[31]	1741774	1			T25	1		T26	1		T27	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	34680369	1			T25	32		T26	32		T27	32
values[0x1]	21056399	1			T28	246		T29	1478		T32	227
transitions[0x0=>0x1]	12621326	1			T28	162		T29	984		T32	122
transitions[0x1=>0x0]	12621181	1			T28	161		T29	984		T32	122

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	1081862	1			T25	1		T26	1		T27	1
all_pins[0]	values[0x1]	659912	1			T28	12		T29	39		T32	9
all_pins[0]	transitions[0x0=>0x1]	409590	1			T28	9		T29	33		T32	5
all_pins[0]	transitions[0x1=>0x0]	407128	1			T29	26		T32	4		T34	4
all_pins[1]	values[0x0]	1081175	1			T25	1		T26	1		T27	1
all_pins[1]	values[0x1]	660599	1			T28	11		T29	49		T32	5
all_pins[1]	transitions[0x0=>0x1]	394633	1			T28	9		T29	28		T34	3
all_pins[1]	transitions[0x1=>0x0]	393946	1			T28	10		T29	18		T32	4
all_pins[2]	values[0x0]	1086686	1			T25	1		T26	1		T27	1
all_pins[2]	values[0x1]	655088	1			T28	8		T29	43		T32	9
all_pins[2]	transitions[0x0=>0x1]	391098	1			T28	6		T29	30		T32	5
all_pins[2]	transitions[0x1=>0x0]	396609	1			T28	9		T29	36		T32	1
all_pins[3]	values[0x0]	1086391	1			T25	1		T26	1		T27	1
all_pins[3]	values[0x1]	655383	1			T28	9		T29	63		T32	5
all_pins[3]	transitions[0x0=>0x1]	392759	1			T28	2		T29	43		T32	3
all_pins[3]	transitions[0x1=>0x0]	392464	1			T28	1		T29	23		T32	7
all_pins[4]	values[0x0]	1078130	1			T25	1		T26	1		T27	1
all_pins[4]	values[0x1]	663644	1			T28	10		T29	19		T32	8
all_pins[4]	transitions[0x0=>0x1]	397264	1			T28	2		T29	9		T32	4
all_pins[4]	transitions[0x1=>0x0]	389003	1			T28	1		T29	53		T32	1
all_pins[5]	values[0x0]	1085191	1			T25	1		T26	1		T27	1
all_pins[5]	values[0x1]	656583	1			T28	14		T29	85		T32	11
all_pins[5]	transitions[0x0=>0x1]	390207	1			T28	10		T29	76		T32	5
all_pins[5]	transitions[0x1=>0x0]	397268	1			T28	6		T29	10		T32	2
all_pins[6]	values[0x0]	1083337	1			T25	1		T26	1		T27	1
all_pins[6]	values[0x1]	658437	1			T28	10		T29	49		T32	9
all_pins[6]	transitions[0x0=>0x1]	395029	1			T28	6		T29	18		T32	3
all_pins[6]	transitions[0x1=>0x0]	393175	1			T28	10		T29	54		T32	5
all_pins[7]	values[0x0]	1084129	1			T25	1		T26	1		T27	1
all_pins[7]	values[0x1]	657645	1			T28	2		T29	23		T32	5
all_pins[7]	transitions[0x0=>0x1]	394860	1			T28	1		T29	3		T32	2
all_pins[7]	transitions[0x1=>0x0]	395652	1			T28	9		T29	29		T32	6
all_pins[8]	values[0x0]	1082512	1			T25	1		T26	1		T27	1
all_pins[8]	values[0x1]	659262	1			T28	8		T29	37		T32	10
all_pins[8]	transitions[0x0=>0x1]	394202	1			T28	7		T29	30		T32	6
all_pins[8]	transitions[0x1=>0x0]	392585	1			T28	1		T29	16		T32	1
all_pins[9]	values[0x0]	1082154	1			T25	1		T26	1		T27	1
all_pins[9]	values[0x1]	659620	1			T28	12		T29	32		T32	10
all_pins[9]	transitions[0x0=>0x1]	396800	1			T28	9		T29	17		T32	5
all_pins[9]	transitions[0x1=>0x0]	396442	1			T28	5		T29	22		T32	5
all_pins[10]	values[0x0]	1083173	1			T25	1		T26	1		T27	1
all_pins[10]	values[0x1]	658601	1			T28	5		T29	41		T32	7
all_pins[10]	transitions[0x0=>0x1]	393353	1			T28	5		T29	41		T32	3
all_pins[10]	transitions[0x1=>0x0]	394372	1			T28	12		T29	32		T32	6
all_pins[11]	values[0x0]	1084232	1			T25	1		T26	1		T27	1
all_pins[11]	values[0x1]	657542	1			T28	3		T29	40		T32	8
all_pins[11]	transitions[0x0=>0x1]	394514	1			T28	2		T29	30		T32	5
all_pins[11]	transitions[0x1=>0x0]	395573	1			T28	4		T29	31		T32	4
all_pins[12]	values[0x0]	1085910	1			T25	1		T26	1		T27	1
all_pins[12]	values[0x1]	655864	1			T28	3		T29	38		T32	7
all_pins[12]	transitions[0x0=>0x1]	393096	1			T28	3		T29	31		T32	4
all_pins[12]	transitions[0x1=>0x0]	394774	1			T28	3		T29	33		T32	5
all_pins[13]	values[0x0]	1083548	1			T25	1		T26	1		T27	1
all_pins[13]	values[0x1]	658226	1			T28	6		T29	46		T32	9
all_pins[13]	transitions[0x0=>0x1]	395489	1			T28	6		T29	27		T32	4
all_pins[13]	transitions[0x1=>0x0]	393127	1			T28	3		T29	19		T32	2
all_pins[14]	values[0x0]	1083539	1			T25	1		T26	1		T27	1
all_pins[14]	values[0x1]	658235	1			T28	12		T29	48		T32	5
all_pins[14]	transitions[0x0=>0x1]	393075	1			T28	7		T29	34		T34	9
all_pins[14]	transitions[0x1=>0x0]	393066	1			T28	1		T29	32		T32	4
all_pins[15]	values[0x0]	1084746	1			T25	1		T26	1		T27	1
all_pins[15]	values[0x1]	657028	1			T28	4		T29	64		T32	7
all_pins[15]	transitions[0x0=>0x1]	392756	1			T28	1		T29	47		T32	5
all_pins[15]	transitions[0x1=>0x0]	393963	1			T28	9		T29	31		T32	3
all_pins[16]	values[0x0]	1081730	1			T25	1		T26	1		T27	1
all_pins[16]	values[0x1]	660044	1			T28	10		T29	66		T32	7
all_pins[16]	transitions[0x0=>0x1]	396517	1			T28	7		T29	36		T32	6
all_pins[16]	transitions[0x1=>0x0]	393501	1			T28	1		T29	34		T32	6
all_pins[17]	values[0x0]	1085369	1			T25	1		T26	1		T27	1
all_pins[17]	values[0x1]	656405	1			T28	12		T29	32		T32	7
all_pins[17]	transitions[0x0=>0x1]	390907	1			T28	8		T29	18		T32	3
all_pins[17]	transitions[0x1=>0x0]	394546	1			T28	6		T29	52		T32	3
all_pins[18]	values[0x0]	1082189	1			T25	1		T26	1		T27	1
all_pins[18]	values[0x1]	659585	1			T28	6		T29	51		T32	5
all_pins[18]	transitions[0x0=>0x1]	395253	1			T28	1		T29	43		T32	2
all_pins[18]	transitions[0x1=>0x0]	392073	1			T28	7		T29	24		T32	4
all_pins[19]	values[0x0]	1084744	1			T25	1		T26	1		T27	1
all_pins[19]	values[0x1]	657030	1			T28	9		T29	28		T32	3
all_pins[19]	transitions[0x0=>0x1]	392931	1			T28	5		T29	15		T32	3
all_pins[19]	transitions[0x1=>0x0]	395486	1			T28	2		T29	38		T32	5
all_pins[20]	values[0x0]	1083468	1			T25	1		T26	1		T27	1
all_pins[20]	values[0x1]	658306	1			T28	4		T29	42		T32	10
all_pins[20]	transitions[0x0=>0x1]	394151	1			T28	1		T29	33		T32	7
all_pins[20]	transitions[0x1=>0x0]	392875	1			T28	6		T29	19		T34	1
all_pins[21]	values[0x0]	1083341	1			T25	1		T26	1		T27	1
all_pins[21]	values[0x1]	658433	1			T28	6		T29	51		T32	6
all_pins[21]	transitions[0x0=>0x1]	392441	1			T28	6		T29	28		T32	2
all_pins[21]	transitions[0x1=>0x0]	392314	1			T28	4		T29	19		T32	6
all_pins[22]	values[0x0]	1083542	1			T25	1		T26	1		T27	1
all_pins[22]	values[0x1]	658232	1			T28	6		T29	64		T32	6
all_pins[22]	transitions[0x0=>0x1]	395140	1			T28	6		T29	28		T32	3
all_pins[22]	transitions[0x1=>0x0]	395341	1			T28	6		T29	15		T32	3
all_pins[23]	values[0x0]	1082899	1			T25	1		T26	1		T27	1
all_pins[23]	values[0x1]	658875	1			T28	7		T29	85		T32	6
all_pins[23]	transitions[0x0=>0x1]	394078	1			T28	5		T29	47		T32	5
all_pins[23]	transitions[0x1=>0x0]	393435	1			T28	4		T29	26		T32	5
all_pins[24]	values[0x0]	1083438	1			T25	1		T26	1		T27	1
all_pins[24]	values[0x1]	658336	1			T28	6		T29	25		T32	7
all_pins[24]	transitions[0x0=>0x1]	394145	1			T28	3		T29	7		T32	3
all_pins[24]	transitions[0x1=>0x0]	394684	1			T28	4		T29	67		T32	2
all_pins[25]	values[0x0]	1082034	1			T25	1		T26	1		T27	1
all_pins[25]	values[0x1]	659740	1			T28	1		T29	69		T32	8
all_pins[25]	transitions[0x0=>0x1]	394388	1			T28	1		T29	52		T32	4
all_pins[25]	transitions[0x1=>0x0]	392984	1			T28	6		T29	8		T32	3
all_pins[26]	values[0x0]	1083399	1			T25	1		T26	1		T27	1
all_pins[26]	values[0x1]	658375	1			T28	16		T29	19		T32	7
all_pins[26]	transitions[0x0=>0x1]	394246	1			T28	15		T29	6		T32	3
all_pins[26]	transitions[0x1=>0x0]	395611	1			T29	56		T32	4		T35	36
all_pins[27]	values[0x0]	1086242	1			T25	1		T26	1		T27	1
all_pins[27]	values[0x1]	655532	1			T28	9		T29	60		T32	6
all_pins[27]	transitions[0x0=>0x1]	393157	1			T28	2		T29	52		T32	3
all_pins[27]	transitions[0x1=>0x0]	396000	1			T28	9		T29	11		T32	4
all_pins[28]	values[0x0]	1087718	1			T25	1		T26	1		T27	1
all_pins[28]	values[0x1]	654056	1			T28	15		T29	53		T32	4
all_pins[28]	transitions[0x0=>0x1]	391901	1			T28	8		T29	42		T32	2
all_pins[28]	transitions[0x1=>0x0]	393377	1			T28	2		T29	49		T32	4
all_pins[29]	values[0x0]	1085772	1			T25	1		T26	1		T27	1
all_pins[29]	values[0x1]	656002	1			T28	3		T29	45		T32	9
all_pins[29]	transitions[0x0=>0x1]	393717	1			T28	3		T29	29		T32	8
all_pins[29]	transitions[0x1=>0x0]	391771	1			T28	15		T29	37		T32	3
all_pins[30]	values[0x0]	1083590	1			T25	1		T26	1		T27	1
all_pins[30]	values[0x1]	658184	1			T28	3		T29	40		T32	4
all_pins[30]	transitions[0x0=>0x1]	394791	1			T28	3		T29	32		T32	3
all_pins[30]	transitions[0x1=>0x0]	392609	1			T28	3		T29	37		T32	8
all_pins[31]	values[0x0]	1084179	1			T25	1		T26	1		T27	1
all_pins[31]	values[0x1]	657595	1			T28	4		T29	32		T32	8
all_pins[31]	transitions[0x0=>0x1]	394838	1			T28	3		T29	19		T32	6
all_pins[31]	transitions[0x1=>0x0]	395427	1			T28	2		T29	27		T32	2