Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	6725402	1			T25	175		T26	138		T27	92
all_values[1]	6725402	1			T25	175		T26	138		T27	92
all_values[2]	6725402	1			T25	175		T26	138		T27	92
all_values[3]	6725402	1			T25	175		T26	138		T27	92
all_values[4]	6725402	1			T25	175		T26	138		T27	92
all_values[5]	6725402	1			T25	175		T26	138		T27	92
all_values[6]	6725402	1			T25	175		T26	138		T27	92
all_values[7]	6725402	1			T25	175		T26	138		T27	92
all_values[8]	6725402	1			T25	175		T26	138		T27	92
all_values[9]	6725402	1			T25	175		T26	138		T27	92
all_values[10]	6725402	1			T25	175		T26	138		T27	92
all_values[11]	6725402	1			T25	175		T26	138		T27	92
all_values[12]	6725402	1			T25	175		T26	138		T27	92
all_values[13]	6725402	1			T25	175		T26	138		T27	92
all_values[14]	6725402	1			T25	175		T26	138		T27	92
all_values[15]	6725402	1			T25	175		T26	138		T27	92
all_values[16]	6725402	1			T25	175		T26	138		T27	92
all_values[17]	6725402	1			T25	175		T26	138		T27	92
all_values[18]	6725402	1			T25	175		T26	138		T27	92
all_values[19]	6725402	1			T25	175		T26	138		T27	92
all_values[20]	6725402	1			T25	175		T26	138		T27	92
all_values[21]	6725402	1			T25	175		T26	138		T27	92
all_values[22]	6725402	1			T25	175		T26	138		T27	92
all_values[23]	6725402	1			T25	175		T26	138		T27	92
all_values[24]	6725402	1			T25	175		T26	138		T27	92
all_values[25]	6725402	1			T25	175		T26	138		T27	92
all_values[26]	6725402	1			T25	175		T26	138		T27	92
all_values[27]	6725402	1			T25	175		T26	138		T27	92
all_values[28]	6725402	1			T25	175		T26	138		T27	92
all_values[29]	6725402	1			T25	175		T26	138		T27	92
all_values[30]	6725402	1			T25	175		T26	138		T27	92
all_values[31]	6725402	1			T25	175		T26	138		T27	92

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

140164535

1

T25

5600

T26

4416

T27

2944

auto[1]

75048329

1

T28

687

T29

3231

T34

486

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

79792447

1

T25

5600

T26

4416

T27

2944

auto[1]

135420417

1

T28

882

T29

6145

T34

561

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

213109409

1

T25

5600

T26

4416

T27

2944

auto[1]

2103455

1

T28

102

T34

72

T35

467

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	2254538	1			T25	175		T26	138		T27	92
all_values[0]	auto[0]	auto[0]	auto[1]	2096996	1			T28	3		T29	134		T34	10
all_values[0]	auto[0]	auto[1]	auto[0]	237552	1			T28	17		T29	5		T34	7
all_values[0]	auto[0]	auto[1]	auto[1]	2070775	1			T28	16		T29	65		T34	5
all_values[0]	auto[1]	auto[0]	auto[1]	32822	1			T28	3		T34	3		T35	10
all_values[0]	auto[1]	auto[1]	auto[1]	32719	1			T28	1		T34	1		T35	7
all_values[1]	auto[0]	auto[0]	auto[0]	2255076	1			T25	175		T26	138		T27	92
all_values[1]	auto[0]	auto[0]	auto[1]	2082184	1			T28	19		T29	109		T34	9
all_values[1]	auto[0]	auto[1]	auto[0]	237679	1			T28	14		T29	17		T34	6
all_values[1]	auto[0]	auto[1]	auto[1]	2084715	1			T28	15		T29	95		T34	2
all_values[1]	auto[1]	auto[0]	auto[1]	33179	1			T28	5		T34	3		T35	2
all_values[1]	auto[1]	auto[1]	auto[1]	32569	1			T28	1		T35	9		T1	19
all_values[2]	auto[0]	auto[0]	auto[0]	2263323	1			T25	175		T26	138		T27	92
all_values[2]	auto[0]	auto[0]	auto[1]	2098698	1			T28	7		T29	116		T34	10
all_values[2]	auto[0]	auto[1]	auto[0]	240025	1			T28	12		T29	9		T34	11
all_values[2]	auto[0]	auto[1]	auto[1]	2057460	1			T28	13		T29	92		T34	6
all_values[2]	auto[1]	auto[0]	auto[1]	33417	1			T28	1		T35	7		T55	1
all_values[2]	auto[1]	auto[1]	auto[1]	32479	1			T28	2		T34	1		T35	4
all_values[3]	auto[0]	auto[0]	auto[0]	2259768	1			T25	175		T26	138		T27	92
all_values[3]	auto[0]	auto[0]	auto[1]	2098977	1			T28	9		T29	77		T34	14
all_values[3]	auto[0]	auto[1]	auto[0]	240574	1			T28	8		T29	28		T34	7
all_values[3]	auto[0]	auto[1]	auto[1]	2060290	1			T28	16		T29	106		T34	5
all_values[3]	auto[1]	auto[0]	auto[1]	33147	1			T28	1		T34	2		T35	4
all_values[3]	auto[1]	auto[1]	auto[1]	32646	1			T28	1		T34	1		T35	9
all_values[4]	auto[0]	auto[0]	auto[0]	2257476	1			T25	175		T26	138		T27	92
all_values[4]	auto[0]	auto[0]	auto[1]	2082095	1			T28	11		T29	162		T34	7
all_values[4]	auto[0]	auto[1]	auto[0]	238365	1			T28	20		T29	15		T34	15
all_values[4]	auto[0]	auto[1]	auto[1]	2081489	1			T28	15		T29	36		T34	5
all_values[4]	auto[1]	auto[0]	auto[1]	32821	1			T28	3		T35	8		T113	6
all_values[4]	auto[1]	auto[1]	auto[1]	33156	1			T28	1		T34	1		T35	11
all_values[5]	auto[0]	auto[0]	auto[0]	2253683	1			T25	175		T26	138		T27	92
all_values[5]	auto[0]	auto[0]	auto[1]	2105834	1			T28	18		T29	42		T34	6
all_values[5]	auto[0]	auto[1]	auto[0]	238546	1			T28	14		T29	29		T34	12
all_values[5]	auto[0]	auto[1]	auto[1]	2061486	1			T28	16		T29	150		T34	5
all_values[5]	auto[1]	auto[0]	auto[1]	33545	1			T28	4		T34	2		T35	12
all_values[5]	auto[1]	auto[1]	auto[1]	32308	1			T35	4		T55	3		T113	1
all_values[6]	auto[0]	auto[0]	auto[0]	2257855	1			T25	175		T26	138		T27	92
all_values[6]	auto[0]	auto[0]	auto[1]	2097272	1			T28	8		T29	72		T34	16
all_values[6]	auto[0]	auto[1]	auto[0]	243383	1			T28	12		T29	27		T34	5
all_values[6]	auto[0]	auto[1]	auto[1]	2061308	1			T28	16		T29	88		T34	2
all_values[6]	auto[1]	auto[0]	auto[1]	33054	1			T28	2		T34	2		T35	5
all_values[6]	auto[1]	auto[1]	auto[1]	32530	1			T34	1		T35	5		T55	2
all_values[7]	auto[0]	auto[0]	auto[0]	2250673	1			T25	175		T26	138		T27	92
all_values[7]	auto[0]	auto[0]	auto[1]	2092191	1			T28	11		T29	123		T34	8
all_values[7]	auto[0]	auto[1]	auto[0]	234243	1			T28	14		T29	17		T34	13
all_values[7]	auto[0]	auto[1]	auto[1]	2082151	1			T28	1		T29	51		T34	12
all_values[7]	auto[1]	auto[0]	auto[1]	33214	1			T28	2		T34	1		T35	10
all_values[7]	auto[1]	auto[1]	auto[1]	32930	1			T28	1		T34	2		T35	4
all_values[8]	auto[0]	auto[0]	auto[0]	2256290	1			T25	175		T26	138		T27	92
all_values[8]	auto[0]	auto[0]	auto[1]	2091536	1			T28	20		T29	107		T34	9
all_values[8]	auto[0]	auto[1]	auto[0]	240774	1			T28	11		T29	20		T34	10
all_values[8]	auto[0]	auto[1]	auto[1]	2071266	1			T28	9		T29	73		T34	7
all_values[8]	auto[1]	auto[0]	auto[1]	32839	1			T28	1		T34	1		T35	12
all_values[8]	auto[1]	auto[1]	auto[1]	32697	1			T35	6		T55	2		T1	13
all_values[9]	auto[0]	auto[0]	auto[0]	2254673	1			T25	175		T26	138		T27	92
all_values[9]	auto[0]	auto[0]	auto[1]	2091336	1			T28	16		T29	133		T34	8
all_values[9]	auto[0]	auto[1]	auto[0]	240362	1			T28	10		T29	11		T34	23
all_values[9]	auto[0]	auto[1]	auto[1]	2073450	1			T28	11		T29	71		T34	4
all_values[9]	auto[1]	auto[0]	auto[1]	32930	1			T28	2		T34	1		T35	8
all_values[9]	auto[1]	auto[1]	auto[1]	32651	1			T28	1		T35	6		T55	2
all_values[10]	auto[0]	auto[0]	auto[0]	2257040	1			T25	175		T26	138		T27	92
all_values[10]	auto[0]	auto[0]	auto[1]	2074438	1			T28	14		T29	136		T34	17
all_values[10]	auto[0]	auto[1]	auto[0]	240575	1			T28	3		T29	4		T34	12
all_values[10]	auto[0]	auto[1]	auto[1]	2088145	1			T28	7		T29	73		T34	4
all_values[10]	auto[1]	auto[0]	auto[1]	32773	1			T28	4		T34	2		T35	7
all_values[10]	auto[1]	auto[1]	auto[1]	32431	1			T34	1		T35	6		T1	15
all_values[11]	auto[0]	auto[0]	auto[0]	2255656	1			T25	175		T26	138		T27	92
all_values[11]	auto[0]	auto[0]	auto[1]	2082652	1			T28	6		T29	125		T34	10
all_values[11]	auto[0]	auto[1]	auto[0]	236087	1			T28	10		T29	15		T34	5
all_values[11]	auto[0]	auto[1]	auto[1]	2085350	1			T28	7		T29	65		T34	5
all_values[11]	auto[1]	auto[0]	auto[1]	32994	1			T28	3		T34	2		T35	9
all_values[11]	auto[1]	auto[1]	auto[1]	32663	1			T28	1		T35	5		T113	2
all_values[12]	auto[0]	auto[0]	auto[0]	2256681	1			T25	175		T26	138		T27	92
all_values[12]	auto[0]	auto[0]	auto[1]	2092345	1			T28	18		T29	93		T34	11
all_values[12]	auto[0]	auto[1]	auto[0]	236699	1			T28	6		T29	21		T34	8
all_values[12]	auto[0]	auto[1]	auto[1]	2074082	1			T28	4		T29	61		T34	4
all_values[12]	auto[1]	auto[0]	auto[1]	32994	1			T28	2		T34	2		T35	7
all_values[12]	auto[1]	auto[1]	auto[1]	32601	1			T35	4		T55	3		T1	15
all_values[13]	auto[0]	auto[0]	auto[0]	2260263	1			T25	175		T26	138		T27	92
all_values[13]	auto[0]	auto[0]	auto[1]	2090206	1			T28	7		T29	119		T34	17
all_values[13]	auto[0]	auto[1]	auto[0]	232896	1			T28	15		T29	20		T34	8
all_values[13]	auto[0]	auto[1]	auto[1]	2076021	1			T28	6		T29	77		T34	1
all_values[13]	auto[1]	auto[0]	auto[1]	33275	1			T28	1		T34	3		T35	5
all_values[13]	auto[1]	auto[1]	auto[1]	32741	1			T28	1		T35	11		T113	1
all_values[14]	auto[0]	auto[0]	auto[0]	2256093	1			T25	175		T26	138		T27	92
all_values[14]	auto[0]	auto[0]	auto[1]	2094585	1			T28	21		T29	103		T34	15
all_values[14]	auto[0]	auto[1]	auto[0]	232596	1			T28	10		T29	18		T34	5
all_values[14]	auto[0]	auto[1]	auto[1]	2076291	1			T28	13		T29	84		T34	11
all_values[14]	auto[1]	auto[0]	auto[1]	33249	1			T28	3		T35	7		T55	3
all_values[14]	auto[1]	auto[1]	auto[1]	32588	1			T34	2		T35	5		T55	2
all_values[15]	auto[0]	auto[0]	auto[0]	2253999	1			T25	175		T26	138		T27	92
all_values[15]	auto[0]	auto[0]	auto[1]	2094173	1			T28	16		T29	53		T34	12
all_values[15]	auto[0]	auto[1]	auto[0]	235995	1			T28	10		T29	31		T34	6
all_values[15]	auto[0]	auto[1]	auto[1]	2075455	1			T28	6		T29	129		T34	3
all_values[15]	auto[1]	auto[0]	auto[1]	32975	1			T28	5		T34	1		T35	12
all_values[15]	auto[1]	auto[1]	auto[1]	32805	1			T35	4		T55	1		T113	2
all_values[16]	auto[0]	auto[0]	auto[0]	2254738	1			T25	175		T26	138		T27	92
all_values[16]	auto[0]	auto[0]	auto[1]	2087383	1			T28	18		T29	77		T34	10
all_values[16]	auto[0]	auto[1]	auto[0]	241948	1			T28	11		T29	15		T34	4
all_values[16]	auto[0]	auto[1]	auto[1]	2075308	1			T28	9		T29	132		T34	8
all_values[16]	auto[1]	auto[0]	auto[1]	33126	1			T28	2		T34	2		T35	11
all_values[16]	auto[1]	auto[1]	auto[1]	32899	1			T28	1		T34	1		T35	6
all_values[17]	auto[0]	auto[0]	auto[0]	2257754	1			T25	175		T26	138		T27	92
all_values[17]	auto[0]	auto[0]	auto[1]	2102088	1			T28	12		T29	157		T34	4
all_values[17]	auto[0]	auto[1]	auto[0]	233298	1			T28	10		T29	6		T34	16
all_values[17]	auto[0]	auto[1]	auto[1]	2066195	1			T28	18		T29	57		T34	5
all_values[17]	auto[1]	auto[0]	auto[1]	33494	1			T28	1		T34	2		T35	10
all_values[17]	auto[1]	auto[1]	auto[1]	32573	1			T28	1		T34	1		T35	4
all_values[18]	auto[0]	auto[0]	auto[0]	2258928	1			T25	175		T26	138		T27	92
all_values[18]	auto[0]	auto[0]	auto[1]	2097784	1			T28	18		T29	88		T34	12
all_values[18]	auto[0]	auto[1]	auto[0]	236837	1			T28	6		T29	26		T34	4
all_values[18]	auto[0]	auto[1]	auto[1]	2066274	1			T28	8		T29	88		T35	83
all_values[18]	auto[1]	auto[0]	auto[1]	33111	1			T28	5		T34	3		T35	12
all_values[18]	auto[1]	auto[1]	auto[1]	32468	1			T28	1		T35	6		T55	1
all_values[19]	auto[0]	auto[0]	auto[0]	2254917	1			T25	175		T26	138		T27	92
all_values[19]	auto[0]	auto[0]	auto[1]	2088521	1			T28	9		T29	125		T34	10
all_values[19]	auto[0]	auto[1]	auto[0]	239630	1			T28	7		T29	18		T34	14
all_values[19]	auto[0]	auto[1]	auto[1]	2076440	1			T28	8		T29	46		T34	2
all_values[19]	auto[1]	auto[0]	auto[1]	33203	1			T28	3		T34	1		T35	10
all_values[19]	auto[1]	auto[1]	auto[1]	32691	1			T28	1		T34	2		T35	6
all_values[20]	auto[0]	auto[0]	auto[0]	2258767	1			T25	175		T26	138		T27	92
all_values[20]	auto[0]	auto[0]	auto[1]	2078837	1			T28	24		T29	100		T34	7
all_values[20]	auto[0]	auto[1]	auto[0]	234962	1			T28	15		T29	29		T34	19
all_values[20]	auto[0]	auto[1]	auto[1]	2087027	1			T28	4		T29	65		T34	7
all_values[20]	auto[1]	auto[0]	auto[1]	32872	1			T28	3		T34	2		T35	10
all_values[20]	auto[1]	auto[1]	auto[1]	32937	1			T35	8		T55	1		T113	1
all_values[21]	auto[0]	auto[0]	auto[0]	2256330	1			T25	175		T26	138		T27	92
all_values[21]	auto[0]	auto[0]	auto[1]	2080888	1			T28	19		T29	128		T34	9
all_values[21]	auto[0]	auto[1]	auto[0]	238412	1			T28	8		T29	6		T34	9
all_values[21]	auto[0]	auto[1]	auto[1]	2084225	1			T28	6		T29	86		T34	4
all_values[21]	auto[1]	auto[0]	auto[1]	32789	1			T28	5		T34	3		T35	13
all_values[21]	auto[1]	auto[1]	auto[1]	32758	1			T35	2		T55	1		T1	14
all_values[22]	auto[0]	auto[0]	auto[0]	2258568	1			T25	175		T26	138		T27	92
all_values[22]	auto[0]	auto[0]	auto[1]	2087238	1			T28	12		T29	85		T34	19
all_values[22]	auto[0]	auto[1]	auto[0]	237075	1			T28	15		T29	11		T34	2
all_values[22]	auto[0]	auto[1]	auto[1]	2076628	1			T28	12		T29	117		T34	2
all_values[22]	auto[1]	auto[0]	auto[1]	33327	1			T28	2		T34	2		T35	10
all_values[22]	auto[1]	auto[1]	auto[1]	32566	1			T28	1		T34	1		T35	6
all_values[23]	auto[0]	auto[0]	auto[0]	2253038	1			T25	175		T26	138		T27	92
all_values[23]	auto[0]	auto[0]	auto[1]	2077573	1			T28	20		T29	28		T34	8
all_values[23]	auto[0]	auto[1]	auto[0]	235212	1			T28	5		T29	30		T34	4
all_values[23]	auto[0]	auto[1]	auto[1]	2093824	1			T28	9		T29	161		T34	9
all_values[23]	auto[1]	auto[0]	auto[1]	32773	1			T28	1		T34	3		T35	7
all_values[23]	auto[1]	auto[1]	auto[1]	32982	1			T28	2		T35	9		T55	1
all_values[24]	auto[0]	auto[0]	auto[0]	2256668	1			T25	175		T26	138		T27	92
all_values[24]	auto[0]	auto[0]	auto[1]	2079512	1			T28	15		T29	153		T34	16
all_values[24]	auto[0]	auto[1]	auto[0]	235926	1			T28	14		T29	12		T34	13
all_values[24]	auto[0]	auto[1]	auto[1]	2087629	1			T28	10		T29	45		T34	4
all_values[24]	auto[1]	auto[0]	auto[1]	32922	1			T28	1		T34	2		T35	11
all_values[24]	auto[1]	auto[1]	auto[1]	32745	1			T28	2		T34	1		T35	3
all_values[25]	auto[0]	auto[0]	auto[0]	2252450	1			T25	175		T26	138		T27	92
all_values[25]	auto[0]	auto[0]	auto[1]	2094028	1			T28	21		T29	88		T34	9
all_values[25]	auto[0]	auto[1]	auto[0]	236011	1			T28	9		T29	16		T34	23
all_values[25]	auto[0]	auto[1]	auto[1]	2077238	1			T29	120		T35	151		T61	821
all_values[25]	auto[1]	auto[0]	auto[1]	32907	1			T28	4		T34	2		T35	7
all_values[25]	auto[1]	auto[1]	auto[1]	32768	1			T28	1		T35	7		T1	9
all_values[26]	auto[0]	auto[0]	auto[0]	2258520	1			T25	175		T26	138		T27	92
all_values[26]	auto[0]	auto[0]	auto[1]	2083671	1			T28	9		T29	173		T34	10
all_values[26]	auto[0]	auto[1]	auto[0]	236412	1			T28	8		T29	4		T34	18
all_values[26]	auto[0]	auto[1]	auto[1]	2081234	1			T28	20		T29	32		T34	3
all_values[26]	auto[1]	auto[0]	auto[1]	33069	1			T28	1		T34	1		T35	9
all_values[26]	auto[1]	auto[1]	auto[1]	32496	1			T28	2		T35	4		T55	1
all_values[27]	auto[0]	auto[0]	auto[0]	2255515	1			T25	175		T26	138		T27	92
all_values[27]	auto[0]	auto[0]	auto[1]	2098506	1			T28	20		T29	86		T34	17
all_values[27]	auto[0]	auto[1]	auto[0]	236571	1			T28	12		T29	9		T34	10
all_values[27]	auto[0]	auto[1]	auto[1]	2069091	1			T28	9		T29	124		T34	3
all_values[27]	auto[1]	auto[0]	auto[1]	33142	1			T28	1		T34	1		T35	9
all_values[27]	auto[1]	auto[1]	auto[1]	32577	1			T28	1		T35	2		T1	19
all_values[28]	auto[0]	auto[0]	auto[0]	2256367	1			T25	175		T26	138		T27	92
all_values[28]	auto[0]	auto[0]	auto[1]	2093364	1			T28	6		T29	124		T34	9
all_values[28]	auto[0]	auto[1]	auto[0]	237174	1			T28	9		T29	7		T34	12
all_values[28]	auto[0]	auto[1]	auto[1]	2073079	1			T28	21		T29	81		T34	6
all_values[28]	auto[1]	auto[0]	auto[1]	33146	1			T34	2		T35	4		T55	2
all_values[28]	auto[1]	auto[1]	auto[1]	32272	1			T35	11		T55	2		T113	1
all_values[29]	auto[0]	auto[0]	auto[0]	2252400	1			T25	175		T26	138		T27	92
all_values[29]	auto[0]	auto[0]	auto[1]	2111311	1			T28	30		T29	140		T34	6
all_values[29]	auto[0]	auto[1]	auto[0]	233213	1			T28	3		T29	13		T34	9
all_values[29]	auto[0]	auto[1]	auto[1]	2062745	1			T28	1		T29	63		T35	51
all_values[29]	auto[1]	auto[0]	auto[1]	33292	1			T28	1		T34	2		T35	8
all_values[29]	auto[1]	auto[1]	auto[1]	32441	1			T28	1		T35	7		T55	1
all_values[30]	auto[0]	auto[0]	auto[0]	2254392	1			T25	175		T26	138		T27	92
all_values[30]	auto[0]	auto[0]	auto[1]	2093109	1			T28	11		T29	101		T34	11
all_values[30]	auto[0]	auto[1]	auto[0]	234678	1			T28	5		T29	29		T34	10
all_values[30]	auto[0]	auto[1]	auto[1]	2077736	1			T28	8		T29	84		T34	3
all_values[30]	auto[1]	auto[0]	auto[1]	33243	1			T28	3		T34	1		T35	11
all_values[30]	auto[1]	auto[1]	auto[1]	32244	1			T35	6		T55	2		T113	1
all_values[31]	auto[0]	auto[0]	auto[0]	2257282	1			T25	175		T26	138		T27	92
all_values[31]	auto[0]	auto[0]	auto[1]	2086797	1			T28	12		T29	101		T34	10
all_values[31]	auto[0]	auto[1]	auto[0]	239016	1			T28	19		T29	26		T34	7
all_values[31]	auto[0]	auto[1]	auto[1]	2076427	1			T28	6		T29	70		T34	6
all_values[31]	auto[1]	auto[0]	auto[1]	33042	1			T28	2		T34	2		T35	4
all_values[31]	auto[1]	auto[1]	auto[1]	32838	1			T28	1		T35	9		T113	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal