Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	6644940	1			T25	344		T26	249		T27	167
bins_for_gpio_bits[1]	6644940	1			T25	344		T26	249		T27	167
bins_for_gpio_bits[2]	6644940	1			T25	344		T26	249		T27	167
bins_for_gpio_bits[3]	6644940	1			T25	344		T26	249		T27	167
bins_for_gpio_bits[4]	6644940	1			T25	344		T26	249		T27	167
bins_for_gpio_bits[5]	6644940	1			T25	344		T26	249		T27	167
bins_for_gpio_bits[6]	6644940	1			T25	344		T26	249		T27	167
bins_for_gpio_bits[7]	6644940	1			T25	344		T26	249		T27	167
bins_for_gpio_bits[8]	6644940	1			T25	344		T26	249		T27	167
bins_for_gpio_bits[9]	6644940	1			T25	344		T26	249		T27	167
bins_for_gpio_bits[10]	6644940	1			T25	344		T26	249		T27	167
bins_for_gpio_bits[11]	6644940	1			T25	344		T26	249		T27	167
bins_for_gpio_bits[12]	6644940	1			T25	344		T26	249		T27	167
bins_for_gpio_bits[13]	6644940	1			T25	344		T26	249		T27	167
bins_for_gpio_bits[14]	6644940	1			T25	344		T26	249		T27	167
bins_for_gpio_bits[15]	6644940	1			T25	344		T26	249		T27	167
bins_for_gpio_bits[16]	6644940	1			T25	344		T26	249		T27	167
bins_for_gpio_bits[17]	6644940	1			T25	344		T26	249		T27	167
bins_for_gpio_bits[18]	6644940	1			T25	344		T26	249		T27	167
bins_for_gpio_bits[19]	6644940	1			T25	344		T26	249		T27	167
bins_for_gpio_bits[20]	6644940	1			T25	344		T26	249		T27	167
bins_for_gpio_bits[21]	6644940	1			T25	344		T26	249		T27	167
bins_for_gpio_bits[22]	6644940	1			T25	344		T26	249		T27	167
bins_for_gpio_bits[23]	6644940	1			T25	344		T26	249		T27	167
bins_for_gpio_bits[24]	6644940	1			T25	344		T26	249		T27	167
bins_for_gpio_bits[25]	6644940	1			T25	344		T26	249		T27	167
bins_for_gpio_bits[26]	6644940	1			T25	344		T26	249		T27	167
bins_for_gpio_bits[27]	6644940	1			T25	344		T26	249		T27	167
bins_for_gpio_bits[28]	6644940	1			T25	344		T26	249		T27	167
bins_for_gpio_bits[29]	6644940	1			T25	344		T26	249		T27	167
bins_for_gpio_bits[30]	6644940	1			T25	344		T26	249		T27	167
bins_for_gpio_bits[31]	6644940	1			T25	344		T26	249		T27	167

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

114104549

1

T25

2570

T26

6310

T27

4338

auto[1]

98533531

1

T25

8438

T26

1658

T27

1006

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

175583743

1

T25

8193

T26

7337

T27

4998

auto[1]

37054337

1

T25

2815

T26

631

T27

346

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

164802277

1

T25

5545

T26

4178

T27

3220

auto[1]

47835803

1

T25

5463

T26

3790

T27

2124

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	2408913	1			T25	22		T26	91		T27	53
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	2155475	1			T25	116		T26	24		T27	13
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	588519	1			T25	56		T26	18		T27	9
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	575766	1			T25	15		T26	73		T27	69
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	340820	1			T25	94		T26	29		T27	19
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	575447	1			T25	41		T26	14		T27	4
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	2397370	1			T25	19		T26	145		T27	78
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	2168650	1			T25	78		T26	30		T27	14
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	579783	1			T25	52		T26	22		T27	9
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	578855	1			T25	13		T26	43		T27	44
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	341566	1			T25	138		T26	7		T27	12
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	578716	1			T25	44		T26	2		T27	10
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	2403564	1			T25	22		T26	130		T27	74
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	2160412	1			T25	140		T26	29		T27	23
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	581674	1			T25	32		T26	10		T27	15
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	579190	1			T25	16		T26	65		T27	42
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	342940	1			T25	114		T26	13		T27	13
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	577160	1			T25	20		T26	2		T28	4
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	2415932	1			T25	12		T26	130		T27	136
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	2152550	1			T25	100		T26	45		T27	20
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	583670	1			T25	31		T26	12		T27	7
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	577450	1			T25	27		T26	49		T27	4
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	341443	1			T25	103		T26	7		T28	8
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	573895	1			T25	71		T26	6		T30	50
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	2411707	1			T25	17		T26	94		T27	113
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	2156446	1			T25	86		T26	33		T27	11
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	587187	1			T25	48		T26	7		T27	9
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	573558	1			T25	26		T26	86		T27	29
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	341037	1			T25	124		T26	18		T27	3
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	575005	1			T25	43		T26	11		T27	2
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	2398343	1			T25	24		T26	78		T27	82
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	2167460	1			T25	110		T26	6		T27	23
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	584284	1			T25	51		T26	6		T27	16
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	578262	1			T25	11		T26	115		T27	40
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	340953	1			T25	81		T26	27		T27	4
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	575638	1			T25	67		T26	17		T27	2
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	2411173	1			T25	18		T26	96		T27	88
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	2159134	1			T25	144		T26	25		T27	29
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	584425	1			T25	33		T26	15		T27	1
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	572939	1			T25	12		T26	83		T27	42
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	340804	1			T25	93		T26	17		T27	3
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	576465	1			T25	44		T26	13		T27	4
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	2412804	1			T25	9		T26	141		T27	98
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	2156853	1			T25	100		T26	40		T27	18
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	582948	1			T25	29		T26	15		T27	2
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	572963	1			T25	30		T26	37		T27	38
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	341088	1			T25	124		T26	10		T27	3
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	578284	1			T25	52		T26	6		T27	8
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	2407227	1			T25	11		T26	38		T27	75
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	2155566	1			T25	89		T26	6		T27	12
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	584200	1			T25	46		T26	2		T27	8
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	577172	1			T25	16		T26	159		T27	55
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	341525	1			T25	127		T26	35		T27	13
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	579250	1			T25	55		T26	9		T27	4
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	2404165	1			T25	31		T26	60		T27	52
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	2156863	1			T25	153		T26	15		T27	23
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	582910	1			T25	74		T26	2		T27	6
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	578748	1			T25	8		T26	133		T27	68
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	345779	1			T25	61		T26	16		T27	9
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	576475	1			T25	17		T26	23		T27	9
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	2402418	1			T25	10		T26	30		T27	37
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	2164317	1			T25	73		T26	8		T27	8
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	584051	1			T25	58		T26	8		T27	5
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	575322	1			T25	24		T26	139		T27	89
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	340895	1			T25	132		T26	45		T27	17
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	577937	1			T25	47		T26	19		T27	11
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	2400770	1			T25	16		T26	101		T27	44
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	2166209	1			T25	101		T26	33		T27	15
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	582063	1			T25	16		T26	7		T28	4
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	577953	1			T25	21		T26	89		T27	75
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	341072	1			T25	159		T26	13		T27	21
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	576873	1			T25	31		T26	6		T27	12
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	2414381	1			T25	17		T26	188		T27	63
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	2157884	1			T25	105		T26	38		T27	14
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	582652	1			T25	34		T26	11		T27	2
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	574305	1			T25	25		T26	12		T27	60
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	342240	1			T25	109		T27	18		T28	8
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	573478	1			T25	54		T27	10		T28	9
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	2407860	1			T25	28		T26	132		T27	77
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	2157791	1			T25	113		T26	32		T27	7
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	585384	1			T25	59		T26	4		T27	2
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	575081	1			T25	19		T26	53		T27	65
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	343912	1			T25	86		T26	10		T27	16
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	574912	1			T25	39		T26	18		T28	2
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	2407030	1			T25	29		T26	130		T27	39
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	2159625	1			T25	141		T26	29		T27	8
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	584067	1			T25	59		T26	18		T27	5
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	576083	1			T25	4		T26	51		T27	94
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	341635	1			T25	63		T26	11		T27	19
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	576500	1			T25	48		T26	10		T27	2
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	2402031	1			T25	19		T26	123		T27	72
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	2166350	1			T25	145		T26	22		T27	23
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	581560	1			T25	57		T26	14		T27	5
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	575762	1			T25	8		T26	79		T27	49
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	343562	1			T25	86		T26	8		T27	8
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	575675	1			T25	29		T26	3		T27	10
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	2403461	1			T25	17		T26	91		T27	66
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	2167105	1			T25	111		T26	23		T27	13
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	583301	1			T25	25		T26	7		T27	7
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	577081	1			T25	30		T26	103		T27	61
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	340357	1			T25	125		T26	23		T27	11
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	573635	1			T25	36		T26	2		T27	9
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	2393934	1			T25	10		T26	112		T27	91
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	2174008	1			T25	92		T26	29		T27	21
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	583639	1			T25	60		T26	13		T27	6
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	578093	1			T25	28		T26	74		T27	42
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	342405	1			T25	109		T26	12		T27	7
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	572861	1			T25	45		T26	9		T30	90
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	2417928	1			T25	13		T26	146		T27	105
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	2145873	1			T25	128		T26	35		T27	23
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	580858	1			T25	41		T26	18		T27	4
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	583096	1			T25	19		T26	41		T27	32
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	345131	1			T25	122		T26	3		T27	1
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	572054	1			T25	21		T26	6		T27	2
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	2403653	1			T25	14		T26	86		T27	94
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	2163685	1			T25	80		T26	8		T27	11
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	578311	1			T25	62		T26	4		T27	11
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	581121	1			T25	24		T26	110		T27	33
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	344025	1			T25	108		T26	29		T27	13
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	574145	1			T25	56		T26	12		T27	5
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	2402387	1			T25	11		T26	53		T27	73
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	2164989	1			T25	99		T26	9		T27	31
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	584763	1			T25	42		T26	9		T27	8
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	576932	1			T25	29		T26	136		T27	48
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	341816	1			T25	106		T26	25		T27	5
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	574053	1			T25	57		T26	17		T27	2
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	2405449	1			T25	20		T26	100		T27	81
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	2158216	1			T25	135		T26	17		T27	9
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	580560	1			T25	45		T26	8		T27	8
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	581757	1			T25	11		T26	87		T27	56
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	343229	1			T25	87		T26	29		T27	13
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	575729	1			T25	46		T26	8		T30	71
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	2400018	1			T25	17		T26	50		T27	73
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	2169401	1			T25	112		T26	9		T27	22
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	580144	1			T25	28		T26	11		T27	2
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	577073	1			T25	26		T26	139		T27	59
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	341734	1			T25	120		T26	31		T27	7
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	576570	1			T25	41		T26	9		T27	4
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	2407653	1			T25	9		T26	75		T27	123
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	2159462	1			T25	44		T26	19		T27	19
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	579592	1			T25	28		T26	7		T27	7
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	577402	1			T25	26		T26	114		T27	17
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	342152	1			T25	173		T26	22		T27	1
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	578679	1			T25	64		T26	12		T28	6
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	2397562	1			T25	23		T26	81		T27	58
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	2169319	1			T25	139		T26	14		T27	9
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	581536	1			T25	37		T26	10		T27	9
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	578289	1			T25	13		T26	108		T27	71
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	343765	1			T25	111		T26	32		T27	18
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	574469	1			T25	21		T26	4		T27	2
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	2409577	1			T25	31		T26	59		T27	69
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	2163821	1			T25	112		T26	20		T27	18
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	582791	1			T25	34		T26	7		T27	5
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	575220	1			T25	11		T26	122		T27	55
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	339436	1			T25	122		T26	25		T27	18
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	574095	1			T25	34		T26	16		T27	2
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	2413266	1			T25	15		T26	149		T27	83
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	2157326	1			T25	144		T26	40		T27	15
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	581247	1			T25	52		T26	7		T27	15
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	575519	1			T25	18		T26	37		T27	39
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	341737	1			T25	81		T26	5		T27	13
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	575845	1			T25	34		T26	11		T27	2
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	2405741	1			T25	15		T26	111		T27	106
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	2161112	1			T25	74		T26	34		T27	24
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	583508	1			T25	36		T26	23		T27	5
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	577912	1			T25	24		T26	68		T27	25
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	341991	1			T25	118		T26	6		T27	1
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	574676	1			T25	77		T26	7		T27	6
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	2404550	1			T25	26		T26	118		T27	52
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	2162870	1			T25	165		T26	30		T27	10
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	580250	1			T25	29		T26	11		T28	5
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	579655	1			T25	11		T26	66		T27	87
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	342388	1			T25	74		T26	12		T27	18
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	575227	1			T25	39		T26	12		T30	80
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	2404320	1			T25	22		T26	44		T27	48
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	2163864	1			T25	97		T26	7		T27	13
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	580781	1			T25	53		T27	2		T28	2
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	581332	1			T25	11		T26	148		T27	81
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	345237	1			T25	110		T26	37		T27	21
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	569406	1			T25	51		T26	13		T27	2
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	2405181	1			T25	15		T26	47		T27	81
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	2167109	1			T25	92		T26	8		T27	13
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	580695	1			T25	33		T26	3		T27	15
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	574345	1			T25	30		T26	151		T27	43
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	344084	1			T25	115		T26	30		T27	13
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	573526	1			T25	59		T26	10		T27	2
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	2411304	1			T25	15		T26	100		T27	90
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	2158050	1			T25	158		T26	16		T27	20
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	581457	1			T25	52		T26	7		T27	9
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	575831	1			T25	15		T26	95		T27	38
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	343451	1			T25	64		T26	23		T27	4
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	574847	1			T25	40		T26	8		T27	6

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal