Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	6644940	1			T25	344		T26	249		T27	167
bins_for_gpio_bits[1]	6644940	1			T25	344		T26	249		T27	167
bins_for_gpio_bits[2]	6644940	1			T25	344		T26	249		T27	167
bins_for_gpio_bits[3]	6644940	1			T25	344		T26	249		T27	167
bins_for_gpio_bits[4]	6644940	1			T25	344		T26	249		T27	167
bins_for_gpio_bits[5]	6644940	1			T25	344		T26	249		T27	167
bins_for_gpio_bits[6]	6644940	1			T25	344		T26	249		T27	167
bins_for_gpio_bits[7]	6644940	1			T25	344		T26	249		T27	167
bins_for_gpio_bits[8]	6644940	1			T25	344		T26	249		T27	167
bins_for_gpio_bits[9]	6644940	1			T25	344		T26	249		T27	167
bins_for_gpio_bits[10]	6644940	1			T25	344		T26	249		T27	167
bins_for_gpio_bits[11]	6644940	1			T25	344		T26	249		T27	167
bins_for_gpio_bits[12]	6644940	1			T25	344		T26	249		T27	167
bins_for_gpio_bits[13]	6644940	1			T25	344		T26	249		T27	167
bins_for_gpio_bits[14]	6644940	1			T25	344		T26	249		T27	167
bins_for_gpio_bits[15]	6644940	1			T25	344		T26	249		T27	167
bins_for_gpio_bits[16]	6644940	1			T25	344		T26	249		T27	167
bins_for_gpio_bits[17]	6644940	1			T25	344		T26	249		T27	167
bins_for_gpio_bits[18]	6644940	1			T25	344		T26	249		T27	167
bins_for_gpio_bits[19]	6644940	1			T25	344		T26	249		T27	167
bins_for_gpio_bits[20]	6644940	1			T25	344		T26	249		T27	167
bins_for_gpio_bits[21]	6644940	1			T25	344		T26	249		T27	167
bins_for_gpio_bits[22]	6644940	1			T25	344		T26	249		T27	167
bins_for_gpio_bits[23]	6644940	1			T25	344		T26	249		T27	167
bins_for_gpio_bits[24]	6644940	1			T25	344		T26	249		T27	167
bins_for_gpio_bits[25]	6644940	1			T25	344		T26	249		T27	167
bins_for_gpio_bits[26]	6644940	1			T25	344		T26	249		T27	167
bins_for_gpio_bits[27]	6644940	1			T25	344		T26	249		T27	167
bins_for_gpio_bits[28]	6644940	1			T25	344		T26	249		T27	167
bins_for_gpio_bits[29]	6644940	1			T25	344		T26	249		T27	167
bins_for_gpio_bits[30]	6644940	1			T25	344		T26	249		T27	167
bins_for_gpio_bits[31]	6644940	1			T25	344		T26	249		T27	167

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

114104549

1

T25

2570

T26

6310

T27

4338

auto[1]

98533531

1

T25

8438

T26

1658

T27

1006

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

114096002

1

T25

2570

T26

6306

T27

4338

auto[1]

98542078

1

T25

8438

T26

1662

T27

1006

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	3469320	1			T25	81		T26	178		T27	129
bins_for_gpio_bits[0]	auto[0]	auto[1]	103553	1			T25	12		T26	4		T27	2
bins_for_gpio_bits[0]	auto[1]	auto[0]	103878	1			T25	12		T26	4		T27	2
bins_for_gpio_bits[0]	auto[1]	auto[1]	2968189	1			T25	239		T26	63		T27	34
bins_for_gpio_bits[1]	auto[0]	auto[0]	3452286	1			T25	77		T26	209		T27	127
bins_for_gpio_bits[1]	auto[0]	auto[1]	103459	1			T25	7		T26	1		T27	4
bins_for_gpio_bits[1]	auto[1]	auto[0]	103722	1			T25	7		T26	1		T27	4
bins_for_gpio_bits[1]	auto[1]	auto[1]	2985473	1			T25	253		T26	38		T27	32
bins_for_gpio_bits[2]	auto[0]	auto[0]	3461029	1			T25	64		T26	204		T27	131
bins_for_gpio_bits[2]	auto[0]	auto[1]	103113	1			T25	6		T26	1		T30	21
bins_for_gpio_bits[2]	auto[1]	auto[0]	103399	1			T25	6		T26	1		T30	21
bins_for_gpio_bits[2]	auto[1]	auto[1]	2977399	1			T25	268		T26	43		T27	36
bins_for_gpio_bits[3]	auto[0]	auto[0]	3473723	1			T25	62		T26	189		T27	147
bins_for_gpio_bits[3]	auto[0]	auto[1]	103058	1			T25	8		T26	2		T30	14
bins_for_gpio_bits[3]	auto[1]	auto[0]	103329	1			T25	8		T26	2		T30	14
bins_for_gpio_bits[3]	auto[1]	auto[1]	2964830	1			T25	266		T26	56		T27	20
bins_for_gpio_bits[4]	auto[0]	auto[0]	3469075	1			T25	82		T26	183		T27	150
bins_for_gpio_bits[4]	auto[0]	auto[1]	103110	1			T25	9		T26	3		T27	1
bins_for_gpio_bits[4]	auto[1]	auto[0]	103377	1			T25	9		T26	4		T27	1
bins_for_gpio_bits[4]	auto[1]	auto[1]	2969378	1			T25	244		T26	59		T27	15
bins_for_gpio_bits[5]	auto[0]	auto[0]	3456874	1			T25	77		T26	194		T27	137
bins_for_gpio_bits[5]	auto[0]	auto[1]	103761	1			T25	9		T26	5		T27	1
bins_for_gpio_bits[5]	auto[1]	auto[0]	104015	1			T25	9		T26	5		T27	1
bins_for_gpio_bits[5]	auto[1]	auto[1]	2980290	1			T25	249		T26	45		T27	28
bins_for_gpio_bits[6]	auto[0]	auto[0]	3464993	1			T25	56		T26	190		T27	130
bins_for_gpio_bits[6]	auto[0]	auto[1]	103268	1			T25	7		T26	4		T27	1
bins_for_gpio_bits[6]	auto[1]	auto[0]	103544	1			T25	7		T26	4		T27	1
bins_for_gpio_bits[6]	auto[1]	auto[1]	2973135	1			T25	274		T26	51		T27	35
bins_for_gpio_bits[7]	auto[0]	auto[0]	3465092	1			T25	64		T26	192		T27	135
bins_for_gpio_bits[7]	auto[0]	auto[1]	103352	1			T25	4		T26	1		T27	3
bins_for_gpio_bits[7]	auto[1]	auto[0]	103623	1			T25	4		T26	1		T27	3
bins_for_gpio_bits[7]	auto[1]	auto[1]	2972873	1			T25	272		T26	55		T27	26
bins_for_gpio_bits[8]	auto[0]	auto[0]	3464723	1			T25	65		T26	195		T27	136
bins_for_gpio_bits[8]	auto[0]	auto[1]	103587	1			T25	8		T26	3		T27	2
bins_for_gpio_bits[8]	auto[1]	auto[0]	103876	1			T25	8		T26	4		T27	2
bins_for_gpio_bits[8]	auto[1]	auto[1]	2972754	1			T25	263		T26	47		T27	27
bins_for_gpio_bits[9]	auto[0]	auto[0]	3462442	1			T25	103		T26	187		T27	122
bins_for_gpio_bits[9]	auto[0]	auto[1]	103159	1			T25	10		T26	8		T27	4
bins_for_gpio_bits[9]	auto[1]	auto[0]	103381	1			T25	10		T26	8		T27	4
bins_for_gpio_bits[9]	auto[1]	auto[1]	2975958	1			T25	221		T26	46		T27	37
bins_for_gpio_bits[10]	auto[0]	auto[0]	3457944	1			T25	84		T26	169		T27	127
bins_for_gpio_bits[10]	auto[0]	auto[1]	103592	1			T25	8		T26	8		T27	4
bins_for_gpio_bits[10]	auto[1]	auto[0]	103847	1			T25	8		T26	8		T27	4
bins_for_gpio_bits[10]	auto[1]	auto[1]	2979557	1			T25	244		T26	64		T27	32
bins_for_gpio_bits[11]	auto[0]	auto[0]	3457122	1			T25	49		T26	194		T27	114
bins_for_gpio_bits[11]	auto[0]	auto[1]	103392	1			T25	4		T26	3		T27	5
bins_for_gpio_bits[11]	auto[1]	auto[0]	103664	1			T25	4		T26	3		T27	5
bins_for_gpio_bits[11]	auto[1]	auto[1]	2980762	1			T25	287		T26	49		T27	43
bins_for_gpio_bits[12]	auto[0]	auto[0]	3468323	1			T25	68		T26	211		T27	121
bins_for_gpio_bits[12]	auto[0]	auto[1]	102711	1			T25	8		T27	4		T30	19
bins_for_gpio_bits[12]	auto[1]	auto[0]	103015	1			T25	8		T27	4		T28	1
bins_for_gpio_bits[12]	auto[1]	auto[1]	2970891	1			T25	260		T26	38		T27	38
bins_for_gpio_bits[13]	auto[0]	auto[0]	3464894	1			T25	98		T26	182		T27	144
bins_for_gpio_bits[13]	auto[0]	auto[1]	103162	1			T25	8		T26	6		T30	20
bins_for_gpio_bits[13]	auto[1]	auto[0]	103431	1			T25	8		T26	7		T30	21
bins_for_gpio_bits[13]	auto[1]	auto[1]	2973453	1			T25	230		T26	54		T27	23
bins_for_gpio_bits[14]	auto[0]	auto[0]	3463846	1			T25	82		T26	195		T27	137
bins_for_gpio_bits[14]	auto[0]	auto[1]	103059	1			T25	10		T26	4		T27	1
bins_for_gpio_bits[14]	auto[1]	auto[0]	103334	1			T25	10		T26	4		T27	1
bins_for_gpio_bits[14]	auto[1]	auto[1]	2974701	1			T25	242		T26	46		T27	28
bins_for_gpio_bits[15]	auto[0]	auto[0]	3456022	1			T25	74		T26	214		T27	122
bins_for_gpio_bits[15]	auto[0]	auto[1]	103104	1			T25	10		T26	1		T27	4
bins_for_gpio_bits[15]	auto[1]	auto[0]	103331	1			T25	10		T26	2		T27	4
bins_for_gpio_bits[15]	auto[1]	auto[1]	2982483	1			T25	250		T26	32		T27	37
bins_for_gpio_bits[16]	auto[0]	auto[0]	3460272	1			T25	66		T26	200		T27	131
bins_for_gpio_bits[16]	auto[0]	auto[1]	103247	1			T25	6		T26	1		T27	3
bins_for_gpio_bits[16]	auto[1]	auto[0]	103571	1			T25	6		T26	1		T27	3
bins_for_gpio_bits[16]	auto[1]	auto[1]	2977850	1			T25	266		T26	47		T27	30
bins_for_gpio_bits[17]	auto[0]	auto[0]	3452309	1			T25	90		T26	197		T27	139
bins_for_gpio_bits[17]	auto[0]	auto[1]	103101	1			T25	8		T26	2		T30	20
bins_for_gpio_bits[17]	auto[1]	auto[0]	103357	1			T25	8		T26	2		T30	20
bins_for_gpio_bits[17]	auto[1]	auto[1]	2986173	1			T25	238		T26	48		T27	28
bins_for_gpio_bits[18]	auto[0]	auto[0]	3478449	1			T25	63		T26	202		T27	140
bins_for_gpio_bits[18]	auto[0]	auto[1]	103152	1			T25	10		T26	3		T27	1
bins_for_gpio_bits[18]	auto[1]	auto[0]	103433	1			T25	10		T26	3		T27	1
bins_for_gpio_bits[18]	auto[1]	auto[1]	2959906	1			T25	261		T26	41		T27	25
bins_for_gpio_bits[19]	auto[0]	auto[0]	3459613	1			T25	93		T26	197		T27	137
bins_for_gpio_bits[19]	auto[0]	auto[1]	103240	1			T25	7		T26	3		T27	1
bins_for_gpio_bits[19]	auto[1]	auto[0]	103472	1			T25	7		T26	3		T27	1
bins_for_gpio_bits[19]	auto[1]	auto[1]	2978615	1			T25	237		T26	46		T27	28
bins_for_gpio_bits[20]	auto[0]	auto[0]	3460480	1			T25	74		T26	194		T27	128
bins_for_gpio_bits[20]	auto[0]	auto[1]	103335	1			T25	8		T26	4		T27	1
bins_for_gpio_bits[20]	auto[1]	auto[0]	103602	1			T25	8		T26	4		T27	1
bins_for_gpio_bits[20]	auto[1]	auto[1]	2977523	1			T25	254		T26	47		T27	37
bins_for_gpio_bits[21]	auto[0]	auto[0]	3464196	1			T25	65		T26	192		T27	145
bins_for_gpio_bits[21]	auto[0]	auto[1]	103293	1			T25	11		T26	3		T30	18
bins_for_gpio_bits[21]	auto[1]	auto[0]	103570	1			T25	11		T26	3		T30	19
bins_for_gpio_bits[21]	auto[1]	auto[1]	2973881	1			T25	257		T26	51		T27	22
bins_for_gpio_bits[22]	auto[0]	auto[0]	3453321	1			T25	65		T26	196		T27	132
bins_for_gpio_bits[22]	auto[0]	auto[1]	103670	1			T25	6		T26	4		T27	2
bins_for_gpio_bits[22]	auto[1]	auto[0]	103914	1			T25	6		T26	4		T27	2
bins_for_gpio_bits[22]	auto[1]	auto[1]	2984035	1			T25	267		T26	45		T27	31
bins_for_gpio_bits[23]	auto[0]	auto[0]	3460808	1			T25	58		T26	190		T27	147
bins_for_gpio_bits[23]	auto[0]	auto[1]	103587	1			T25	5		T26	6		T30	19
bins_for_gpio_bits[23]	auto[1]	auto[0]	103839	1			T25	5		T26	6		T30	19
bins_for_gpio_bits[23]	auto[1]	auto[1]	2976706	1			T25	276		T26	47		T27	20
bins_for_gpio_bits[24]	auto[0]	auto[0]	3453675	1			T25	66		T26	197		T27	137
bins_for_gpio_bits[24]	auto[0]	auto[1]	103467	1			T25	7		T26	2		T27	1
bins_for_gpio_bits[24]	auto[1]	auto[0]	103712	1			T25	7		T26	2		T27	1
bins_for_gpio_bits[24]	auto[1]	auto[1]	2984086	1			T25	264		T26	48		T27	28
bins_for_gpio_bits[25]	auto[0]	auto[0]	3464023	1			T25	66		T26	183		T27	128
bins_for_gpio_bits[25]	auto[0]	auto[1]	103308	1			T25	10		T26	5		T27	1
bins_for_gpio_bits[25]	auto[1]	auto[0]	103565	1			T25	10		T26	5		T27	1
bins_for_gpio_bits[25]	auto[1]	auto[1]	2974044	1			T25	258		T26	56		T27	37
bins_for_gpio_bits[26]	auto[0]	auto[0]	3466446	1			T25	78		T26	191		T27	136
bins_for_gpio_bits[26]	auto[0]	auto[1]	103383	1			T25	7		T26	2		T27	1
bins_for_gpio_bits[26]	auto[1]	auto[0]	103586	1			T25	7		T26	2		T27	1
bins_for_gpio_bits[26]	auto[1]	auto[1]	2971525	1			T25	252		T26	54		T27	29
bins_for_gpio_bits[27]	auto[0]	auto[0]	3463562	1			T25	69		T26	200		T27	134
bins_for_gpio_bits[27]	auto[0]	auto[1]	103328	1			T25	6		T26	2		T27	2
bins_for_gpio_bits[27]	auto[1]	auto[0]	103599	1			T25	6		T26	2		T27	2
bins_for_gpio_bits[27]	auto[1]	auto[1]	2974451	1			T25	263		T26	45		T27	29
bins_for_gpio_bits[28]	auto[0]	auto[0]	3460721	1			T25	59		T26	191		T27	139
bins_for_gpio_bits[28]	auto[0]	auto[1]	103474	1			T25	7		T26	4		T30	20
bins_for_gpio_bits[28]	auto[1]	auto[0]	103734	1			T25	7		T26	4		T30	20
bins_for_gpio_bits[28]	auto[1]	auto[1]	2977011	1			T25	271		T26	50		T27	28
bins_for_gpio_bits[29]	auto[0]	auto[0]	3463325	1			T25	75		T26	188		T27	130
bins_for_gpio_bits[29]	auto[0]	auto[1]	102816	1			T25	11		T26	4		T27	1
bins_for_gpio_bits[29]	auto[1]	auto[0]	103108	1			T25	11		T26	4		T27	1
bins_for_gpio_bits[29]	auto[1]	auto[1]	2975691	1			T25	247		T26	53		T27	35
bins_for_gpio_bits[30]	auto[0]	auto[0]	3457048	1			T25	68		T26	198		T27	138
bins_for_gpio_bits[30]	auto[0]	auto[1]	102900	1			T25	10		T26	3		T27	1
bins_for_gpio_bits[30]	auto[1]	auto[0]	103173	1			T25	10		T26	3		T27	1
bins_for_gpio_bits[30]	auto[1]	auto[1]	2981819	1			T25	256		T26	45		T27	27
bins_for_gpio_bits[31]	auto[0]	auto[0]	3464681	1			T25	71		T26	198		T27	135
bins_for_gpio_bits[31]	auto[0]	auto[1]	103624	1			T25	11		T26	4		T27	2
bins_for_gpio_bits[31]	auto[1]	auto[0]	103911	1			T25	11		T26	4		T27	2
bins_for_gpio_bits[31]	auto[1]	auto[1]	2972724	1			T25	251		T26	43		T27	28