Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4384356 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
| auto[1] |
2341046 |
1 |
|
|
T28 |
34 |
|
T29 |
70 |
|
T34 |
13 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6430935 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
| auto[1] |
294467 |
1 |
|
|
T28 |
1 |
|
T29 |
14 |
|
T34 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4379973 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
| auto[1] |
2345429 |
1 |
|
|
T28 |
19 |
|
T29 |
168 |
|
T34 |
14 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1032114 |
1 |
|
|
T28 |
10 |
|
T29 |
113 |
|
T34 |
9 |
| auto[1] |
auto[0] |
auto[1] |
148349 |
1 |
|
|
T29 |
9 |
|
T34 |
1 |
|
T35 |
4 |
| auto[1] |
auto[1] |
auto[0] |
1018848 |
1 |
|
|
T28 |
8 |
|
T29 |
41 |
|
T34 |
4 |
| auto[1] |
auto[1] |
auto[1] |
146118 |
1 |
|
|
T28 |
1 |
|
T29 |
5 |
|
T35 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4370439 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
| auto[1] |
2354963 |
1 |
|
|
T28 |
30 |
|
T29 |
112 |
|
T34 |
8 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6431192 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
| auto[1] |
294210 |
1 |
|
|
T29 |
6 |
|
T35 |
8 |
|
T61 |
194 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4389250 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
| auto[1] |
2336152 |
1 |
|
|
T28 |
25 |
|
T29 |
98 |
|
T34 |
15 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1020975 |
1 |
|
|
T28 |
14 |
|
T29 |
40 |
|
T34 |
12 |
| auto[1] |
auto[0] |
auto[1] |
147469 |
1 |
|
|
T29 |
4 |
|
T35 |
2 |
|
T61 |
130 |
| auto[1] |
auto[1] |
auto[0] |
1020967 |
1 |
|
|
T28 |
11 |
|
T29 |
52 |
|
T34 |
3 |
| auto[1] |
auto[1] |
auto[1] |
146741 |
1 |
|
|
T29 |
2 |
|
T35 |
6 |
|
T61 |
64 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4364251 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
| auto[1] |
2361151 |
1 |
|
|
T28 |
10 |
|
T29 |
77 |
|
T34 |
17 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6428575 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
| auto[1] |
296827 |
1 |
|
|
T29 |
7 |
|
T34 |
1 |
|
T35 |
7 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4371970 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
| auto[1] |
2353432 |
1 |
|
|
T28 |
8 |
|
T29 |
133 |
|
T34 |
22 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1027992 |
1 |
|
|
T28 |
8 |
|
T29 |
94 |
|
T34 |
14 |
| auto[1] |
auto[0] |
auto[1] |
148562 |
1 |
|
|
T29 |
4 |
|
T34 |
1 |
|
T35 |
3 |
| auto[1] |
auto[1] |
auto[0] |
1028613 |
1 |
|
|
T29 |
32 |
|
T34 |
7 |
|
T35 |
82 |
| auto[1] |
auto[1] |
auto[1] |
148265 |
1 |
|
|
T29 |
3 |
|
T35 |
4 |
|
T61 |
46 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4371302 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
| auto[1] |
2354100 |
1 |
|
|
T28 |
18 |
|
T29 |
80 |
|
T34 |
10 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6429346 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
| auto[1] |
296056 |
1 |
|
|
T28 |
1 |
|
T29 |
3 |
|
T34 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4375196 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
| auto[1] |
2350206 |
1 |
|
|
T28 |
21 |
|
T29 |
40 |
|
T34 |
10 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1028536 |
1 |
|
|
T28 |
10 |
|
T29 |
7 |
|
T34 |
9 |
| auto[1] |
auto[0] |
auto[1] |
147774 |
1 |
|
|
T34 |
1 |
|
T35 |
3 |
|
T61 |
25 |
| auto[1] |
auto[1] |
auto[0] |
1025614 |
1 |
|
|
T28 |
10 |
|
T29 |
30 |
|
T35 |
37 |
| auto[1] |
auto[1] |
auto[1] |
148282 |
1 |
|
|
T28 |
1 |
|
T29 |
3 |
|
T35 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4382020 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
| auto[1] |
2343382 |
1 |
|
|
T28 |
10 |
|
T29 |
82 |
|
T34 |
12 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6432215 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
| auto[1] |
293187 |
1 |
|
|
T29 |
3 |
|
T34 |
1 |
|
T35 |
9 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4383608 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
| auto[1] |
2341794 |
1 |
|
|
T28 |
17 |
|
T29 |
98 |
|
T34 |
29 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1027825 |
1 |
|
|
T28 |
17 |
|
T29 |
60 |
|
T34 |
18 |
| auto[1] |
auto[0] |
auto[1] |
147056 |
1 |
|
|
T29 |
2 |
|
T34 |
1 |
|
T35 |
8 |
| auto[1] |
auto[1] |
auto[0] |
1020782 |
1 |
|
|
T29 |
35 |
|
T34 |
10 |
|
T35 |
52 |
| auto[1] |
auto[1] |
auto[1] |
146131 |
1 |
|
|
T29 |
1 |
|
T35 |
1 |
|
T61 |
62 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4383744 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
| auto[1] |
2341658 |
1 |
|
|
T28 |
22 |
|
T29 |
97 |
|
T34 |
9 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6431323 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
| auto[1] |
294079 |
1 |
|
|
T28 |
1 |
|
T29 |
9 |
|
T35 |
7 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4382783 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
| auto[1] |
2342619 |
1 |
|
|
T28 |
23 |
|
T29 |
130 |
|
T34 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1028057 |
1 |
|
|
T28 |
19 |
|
T29 |
76 |
|
T35 |
75 |
| auto[1] |
auto[0] |
auto[1] |
147879 |
1 |
|
|
T28 |
1 |
|
T29 |
5 |
|
T35 |
5 |
| auto[1] |
auto[1] |
auto[0] |
1020483 |
1 |
|
|
T28 |
3 |
|
T29 |
45 |
|
T34 |
3 |
| auto[1] |
auto[1] |
auto[1] |
146200 |
1 |
|
|
T29 |
4 |
|
T35 |
2 |
|
T61 |
73 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4383927 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
| auto[1] |
2341475 |
1 |
|
|
T28 |
23 |
|
T29 |
102 |
|
T34 |
18 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6428594 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
| auto[1] |
296808 |
1 |
|
|
T28 |
1 |
|
T29 |
11 |
|
T35 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4368989 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
| auto[1] |
2356413 |
1 |
|
|
T28 |
24 |
|
T29 |
110 |
|
T34 |
18 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1039180 |
1 |
|
|
T28 |
23 |
|
T29 |
64 |
|
T34 |
10 |
| auto[1] |
auto[0] |
auto[1] |
149981 |
1 |
|
|
T28 |
1 |
|
T29 |
6 |
|
T35 |
3 |
| auto[1] |
auto[1] |
auto[0] |
1020425 |
1 |
|
|
T29 |
35 |
|
T34 |
8 |
|
T35 |
67 |
| auto[1] |
auto[1] |
auto[1] |
146827 |
1 |
|
|
T29 |
5 |
|
T35 |
1 |
|
T61 |
33 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4381147 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
| auto[1] |
2344255 |
1 |
|
|
T28 |
16 |
|
T29 |
160 |
|
T34 |
9 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6430017 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
| auto[1] |
295385 |
1 |
|
|
T29 |
4 |
|
T34 |
1 |
|
T35 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4382829 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
| auto[1] |
2342573 |
1 |
|
|
T28 |
18 |
|
T29 |
111 |
|
T34 |
15 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1030264 |
1 |
|
|
T28 |
18 |
|
T29 |
36 |
|
T34 |
9 |
| auto[1] |
auto[0] |
auto[1] |
149041 |
1 |
|
|
T29 |
2 |
|
T34 |
1 |
|
T35 |
3 |
| auto[1] |
auto[1] |
auto[0] |
1016924 |
1 |
|
|
T29 |
71 |
|
T34 |
5 |
|
T35 |
12 |
| auto[1] |
auto[1] |
auto[1] |
146344 |
1 |
|
|
T29 |
2 |
|
T35 |
1 |
|
T61 |
42 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4375247 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
| auto[1] |
2350155 |
1 |
|
|
T28 |
21 |
|
T29 |
147 |
|
T34 |
13 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6429128 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
| auto[1] |
296274 |
1 |
|
|
T29 |
6 |
|
T35 |
6 |
|
T61 |
121 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4372033 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
| auto[1] |
2353369 |
1 |
|
|
T28 |
28 |
|
T29 |
92 |
|
T34 |
22 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1035359 |
1 |
|
|
T28 |
28 |
|
T29 |
18 |
|
T34 |
11 |
| auto[1] |
auto[0] |
auto[1] |
149207 |
1 |
|
|
T29 |
2 |
|
T35 |
2 |
|
T61 |
58 |
| auto[1] |
auto[1] |
auto[0] |
1021736 |
1 |
|
|
T29 |
68 |
|
T34 |
11 |
|
T35 |
87 |
| auto[1] |
auto[1] |
auto[1] |
147067 |
1 |
|
|
T29 |
4 |
|
T35 |
4 |
|
T61 |
63 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4393336 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
| auto[1] |
2332066 |
1 |
|
|
T28 |
29 |
|
T29 |
63 |
|
T34 |
22 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6429869 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
| auto[1] |
295533 |
1 |
|
|
T29 |
12 |
|
T35 |
5 |
|
T61 |
193 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4374138 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
| auto[1] |
2351264 |
1 |
|
|
T28 |
2 |
|
T29 |
154 |
|
T34 |
18 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1037873 |
1 |
|
|
T29 |
84 |
|
T34 |
10 |
|
T35 |
93 |
| auto[1] |
auto[0] |
auto[1] |
148631 |
1 |
|
|
T29 |
7 |
|
T35 |
2 |
|
T61 |
73 |
| auto[1] |
auto[1] |
auto[0] |
1017858 |
1 |
|
|
T28 |
2 |
|
T29 |
58 |
|
T34 |
8 |
| auto[1] |
auto[1] |
auto[1] |
146902 |
1 |
|
|
T29 |
5 |
|
T35 |
3 |
|
T61 |
120 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4389823 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
| auto[1] |
2335579 |
1 |
|
|
T28 |
15 |
|
T29 |
114 |
|
T34 |
4 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6432524 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
| auto[1] |
292878 |
1 |
|
|
T29 |
6 |
|
T35 |
5 |
|
T61 |
135 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4391855 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
| auto[1] |
2333547 |
1 |
|
|
T28 |
8 |
|
T29 |
93 |
|
T34 |
11 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1021931 |
1 |
|
|
T28 |
6 |
|
T29 |
52 |
|
T34 |
11 |
| auto[1] |
auto[0] |
auto[1] |
147117 |
1 |
|
|
T29 |
5 |
|
T35 |
2 |
|
T61 |
62 |
| auto[1] |
auto[1] |
auto[0] |
1018738 |
1 |
|
|
T28 |
2 |
|
T29 |
35 |
|
T35 |
58 |
| auto[1] |
auto[1] |
auto[1] |
145761 |
1 |
|
|
T29 |
1 |
|
T35 |
3 |
|
T61 |
73 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4376641 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
| auto[1] |
2348761 |
1 |
|
|
T28 |
16 |
|
T29 |
64 |
|
T34 |
18 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6427449 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
| auto[1] |
297953 |
1 |
|
|
T29 |
9 |
|
T35 |
10 |
|
T61 |
170 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4365681 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
| auto[1] |
2359721 |
1 |
|
|
T28 |
12 |
|
T29 |
138 |
|
T34 |
10 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1034702 |
1 |
|
|
T28 |
12 |
|
T29 |
91 |
|
T34 |
10 |
| auto[1] |
auto[0] |
auto[1] |
150220 |
1 |
|
|
T29 |
9 |
|
T35 |
5 |
|
T61 |
91 |
| auto[1] |
auto[1] |
auto[0] |
1027066 |
1 |
|
|
T29 |
38 |
|
T35 |
98 |
|
T61 |
334 |
| auto[1] |
auto[1] |
auto[1] |
147733 |
1 |
|
|
T35 |
5 |
|
T61 |
79 |
|
T114 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4395438 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
| auto[1] |
2329964 |
1 |
|
|
T28 |
27 |
|
T29 |
101 |
|
T34 |
18 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6433033 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
| auto[1] |
292369 |
1 |
|
|
T29 |
6 |
|
T35 |
5 |
|
T61 |
139 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4398369 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
| auto[1] |
2327033 |
1 |
|
|
T28 |
20 |
|
T29 |
89 |
|
T34 |
15 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1023404 |
1 |
|
|
T28 |
10 |
|
T29 |
59 |
|
T34 |
7 |
| auto[1] |
auto[0] |
auto[1] |
147194 |
1 |
|
|
T29 |
5 |
|
T35 |
4 |
|
T61 |
79 |
| auto[1] |
auto[1] |
auto[0] |
1011260 |
1 |
|
|
T28 |
10 |
|
T29 |
24 |
|
T34 |
8 |
| auto[1] |
auto[1] |
auto[1] |
145175 |
1 |
|
|
T29 |
1 |
|
T35 |
1 |
|
T61 |
60 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4370476 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
| auto[1] |
2354926 |
1 |
|
|
T28 |
19 |
|
T29 |
94 |
|
T34 |
26 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6426939 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
| auto[1] |
298463 |
1 |
|
|
T29 |
2 |
|
T35 |
6 |
|
T61 |
151 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4358850 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
| auto[1] |
2366552 |
1 |
|
|
T28 |
29 |
|
T29 |
98 |
|
T34 |
11 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1033309 |
1 |
|
|
T28 |
24 |
|
T29 |
54 |
|
T35 |
110 |
| auto[1] |
auto[0] |
auto[1] |
149043 |
1 |
|
|
T35 |
3 |
|
T61 |
78 |
|
T55 |
1 |
| auto[1] |
auto[1] |
auto[0] |
1034780 |
1 |
|
|
T28 |
5 |
|
T29 |
42 |
|
T34 |
11 |
| auto[1] |
auto[1] |
auto[1] |
149420 |
1 |
|
|
T29 |
2 |
|
T35 |
3 |
|
T61 |
73 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4370007 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
| auto[1] |
2355395 |
1 |
|
|
T28 |
14 |
|
T29 |
92 |
|
T34 |
13 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6432405 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
| auto[1] |
292997 |
1 |
|
|
T29 |
8 |
|
T35 |
5 |
|
T61 |
161 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4396110 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
| auto[1] |
2329292 |
1 |
|
|
T28 |
23 |
|
T29 |
105 |
|
T34 |
19 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1013114 |
1 |
|
|
T28 |
18 |
|
T29 |
55 |
|
T34 |
9 |
| auto[1] |
auto[0] |
auto[1] |
145493 |
1 |
|
|
T29 |
5 |
|
T35 |
5 |
|
T61 |
60 |
| auto[1] |
auto[1] |
auto[0] |
1023181 |
1 |
|
|
T28 |
5 |
|
T29 |
42 |
|
T34 |
10 |
| auto[1] |
auto[1] |
auto[1] |
147504 |
1 |
|
|
T29 |
3 |
|
T61 |
101 |
|
T55 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4379133 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
| auto[1] |
2346269 |
1 |
|
|
T28 |
28 |
|
T29 |
128 |
|
T34 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6428931 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
| auto[1] |
296471 |
1 |
|
|
T29 |
5 |
|
T35 |
7 |
|
T61 |
131 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4373353 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
| auto[1] |
2352049 |
1 |
|
|
T28 |
12 |
|
T29 |
84 |
|
T34 |
11 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1033651 |
1 |
|
|
T28 |
8 |
|
T29 |
34 |
|
T34 |
11 |
| auto[1] |
auto[0] |
auto[1] |
149541 |
1 |
|
|
T29 |
1 |
|
T35 |
4 |
|
T61 |
76 |
| auto[1] |
auto[1] |
auto[0] |
1021927 |
1 |
|
|
T28 |
4 |
|
T29 |
45 |
|
T35 |
67 |
| auto[1] |
auto[1] |
auto[1] |
146930 |
1 |
|
|
T29 |
4 |
|
T35 |
3 |
|
T61 |
55 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4363384 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
| auto[1] |
2362018 |
1 |
|
|
T28 |
16 |
|
T29 |
191 |
|
T34 |
13 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6429024 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
| auto[1] |
296378 |
1 |
|
|
T29 |
8 |
|
T34 |
1 |
|
T35 |
8 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4373835 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
| auto[1] |
2351567 |
1 |
|
|
T28 |
6 |
|
T29 |
118 |
|
T34 |
10 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1029482 |
1 |
|
|
T28 |
6 |
|
T29 |
10 |
|
T34 |
3 |
| auto[1] |
auto[0] |
auto[1] |
148389 |
1 |
|
|
T34 |
1 |
|
T35 |
3 |
|
T61 |
73 |
| auto[1] |
auto[1] |
auto[0] |
1025707 |
1 |
|
|
T29 |
100 |
|
T34 |
6 |
|
T35 |
110 |
| auto[1] |
auto[1] |
auto[1] |
147989 |
1 |
|
|
T29 |
8 |
|
T35 |
5 |
|
T61 |
56 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |