Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4379385 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
| auto[1] |
2346017 |
1 |
|
|
T28 |
10 |
|
T29 |
136 |
|
T34 |
23 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6430138 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
| auto[1] |
295264 |
1 |
|
|
T29 |
16 |
|
T35 |
6 |
|
T61 |
152 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4374039 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
| auto[1] |
2351363 |
1 |
|
|
T28 |
18 |
|
T29 |
172 |
|
T34 |
14 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1029135 |
1 |
|
|
T28 |
18 |
|
T29 |
59 |
|
T34 |
6 |
| auto[1] |
auto[0] |
auto[1] |
147568 |
1 |
|
|
T29 |
7 |
|
T35 |
2 |
|
T61 |
76 |
| auto[1] |
auto[1] |
auto[0] |
1026964 |
1 |
|
|
T29 |
97 |
|
T34 |
8 |
|
T35 |
72 |
| auto[1] |
auto[1] |
auto[1] |
147696 |
1 |
|
|
T29 |
9 |
|
T35 |
4 |
|
T61 |
76 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |