Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4370476 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
| auto[1] |
2354926 |
1 |
|
|
T28 |
19 |
|
T29 |
94 |
|
T34 |
26 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5632541 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
| auto[1] |
1092861 |
1 |
|
|
T29 |
71 |
|
T34 |
12 |
|
T35 |
35 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4371824 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
| auto[1] |
2353578 |
1 |
|
|
T28 |
16 |
|
T29 |
102 |
|
T34 |
14 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
632313 |
1 |
|
|
T28 |
15 |
|
T29 |
15 |
|
T34 |
2 |
| auto[1] |
auto[0] |
auto[1] |
548978 |
1 |
|
|
T29 |
47 |
|
T34 |
5 |
|
T35 |
20 |
| auto[1] |
auto[1] |
auto[0] |
628404 |
1 |
|
|
T28 |
1 |
|
T29 |
16 |
|
T35 |
39 |
| auto[1] |
auto[1] |
auto[1] |
543883 |
1 |
|
|
T29 |
24 |
|
T34 |
7 |
|
T35 |
15 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |