Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4370007 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
| auto[1] |
2355395 |
1 |
|
|
T28 |
14 |
|
T29 |
92 |
|
T34 |
13 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5644736 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
| auto[1] |
1080666 |
1 |
|
|
T29 |
75 |
|
T34 |
2 |
|
T35 |
26 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4399856 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
| auto[1] |
2325546 |
1 |
|
|
T28 |
12 |
|
T29 |
122 |
|
T34 |
9 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
618527 |
1 |
|
|
T28 |
11 |
|
T29 |
32 |
|
T34 |
5 |
| auto[1] |
auto[0] |
auto[1] |
541116 |
1 |
|
|
T29 |
43 |
|
T34 |
2 |
|
T35 |
22 |
| auto[1] |
auto[1] |
auto[0] |
626353 |
1 |
|
|
T28 |
1 |
|
T29 |
15 |
|
T34 |
2 |
| auto[1] |
auto[1] |
auto[1] |
539550 |
1 |
|
|
T29 |
32 |
|
T35 |
4 |
|
T61 |
97 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |