Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4379133 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
| auto[1] |
2346269 |
1 |
|
|
T28 |
28 |
|
T29 |
128 |
|
T34 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5625806 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
| auto[1] |
1099596 |
1 |
|
|
T29 |
80 |
|
T34 |
2 |
|
T35 |
26 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4365593 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
| auto[1] |
2359809 |
1 |
|
|
T28 |
9 |
|
T29 |
139 |
|
T34 |
7 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
628943 |
1 |
|
|
T28 |
5 |
|
T29 |
24 |
|
T34 |
5 |
| auto[1] |
auto[0] |
auto[1] |
551161 |
1 |
|
|
T29 |
29 |
|
T34 |
2 |
|
T35 |
12 |
| auto[1] |
auto[1] |
auto[0] |
631270 |
1 |
|
|
T28 |
4 |
|
T29 |
35 |
|
T35 |
55 |
| auto[1] |
auto[1] |
auto[1] |
548435 |
1 |
|
|
T29 |
51 |
|
T35 |
14 |
|
T61 |
125 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |