Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4378939 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
auto[1] |
2346463 |
1 |
|
|
T28 |
22 |
|
T29 |
82 |
|
T34 |
27 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
5637028 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
auto[1] |
1088374 |
1 |
|
|
T28 |
3 |
|
T29 |
52 |
|
T34 |
2 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4383285 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
auto[1] |
2342117 |
1 |
|
|
T28 |
16 |
|
T29 |
95 |
|
T34 |
6 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
631145 |
1 |
|
|
T28 |
12 |
|
T29 |
30 |
|
T34 |
2 |
auto[1] |
auto[0] |
auto[1] |
545150 |
1 |
|
|
T28 |
3 |
|
T29 |
45 |
|
T34 |
2 |
auto[1] |
auto[1] |
auto[0] |
622598 |
1 |
|
|
T28 |
1 |
|
T29 |
13 |
|
T34 |
2 |
auto[1] |
auto[1] |
auto[1] |
543224 |
1 |
|
|
T29 |
7 |
|
T35 |
10 |
|
T61 |
289 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4384356 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
auto[1] |
2341046 |
1 |
|
|
T28 |
34 |
|
T29 |
70 |
|
T34 |
13 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
5472825 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
auto[1] |
1252577 |
1 |
|
|
T29 |
40 |
|
T34 |
2 |
|
T35 |
171 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4387677 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
auto[1] |
2337725 |
1 |
|
|
T28 |
13 |
|
T29 |
92 |
|
T34 |
15 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
546529 |
1 |
|
|
T28 |
6 |
|
T29 |
47 |
|
T34 |
9 |
auto[1] |
auto[0] |
auto[1] |
629459 |
1 |
|
|
T29 |
23 |
|
T34 |
2 |
|
T35 |
59 |
auto[1] |
auto[1] |
auto[0] |
538619 |
1 |
|
|
T28 |
7 |
|
T29 |
5 |
|
T34 |
4 |
auto[1] |
auto[1] |
auto[1] |
623118 |
1 |
|
|
T29 |
17 |
|
T35 |
112 |
|
T61 |
178 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4370439 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
auto[1] |
2354963 |
1 |
|
|
T28 |
30 |
|
T29 |
112 |
|
T34 |
8 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
5470646 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
auto[1] |
1254756 |
1 |
|
|
T28 |
23 |
|
T29 |
54 |
|
T34 |
5 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4378454 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
auto[1] |
2346948 |
1 |
|
|
T28 |
28 |
|
T29 |
106 |
|
T34 |
9 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
544752 |
1 |
|
|
T28 |
5 |
|
T29 |
35 |
|
T34 |
4 |
auto[1] |
auto[0] |
auto[1] |
628340 |
1 |
|
|
T28 |
13 |
|
T29 |
32 |
|
T34 |
5 |
auto[1] |
auto[1] |
auto[0] |
547440 |
1 |
|
|
T29 |
17 |
|
T35 |
32 |
|
T61 |
222 |
auto[1] |
auto[1] |
auto[1] |
626416 |
1 |
|
|
T28 |
10 |
|
T29 |
22 |
|
T35 |
103 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4364251 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
auto[1] |
2361151 |
1 |
|
|
T28 |
10 |
|
T29 |
77 |
|
T34 |
17 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
5476591 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
auto[1] |
1248811 |
1 |
|
|
T28 |
6 |
|
T29 |
79 |
|
T34 |
1 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4393809 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
auto[1] |
2331593 |
1 |
|
|
T28 |
28 |
|
T29 |
130 |
|
T34 |
22 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
540656 |
1 |
|
|
T28 |
16 |
|
T29 |
27 |
|
T34 |
20 |
auto[1] |
auto[0] |
auto[1] |
623697 |
1 |
|
|
T28 |
6 |
|
T29 |
50 |
|
T34 |
1 |
auto[1] |
auto[1] |
auto[0] |
542126 |
1 |
|
|
T28 |
6 |
|
T29 |
24 |
|
T34 |
1 |
auto[1] |
auto[1] |
auto[1] |
625114 |
1 |
|
|
T29 |
29 |
|
T35 |
75 |
|
T61 |
108 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4371302 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
auto[1] |
2354100 |
1 |
|
|
T28 |
18 |
|
T29 |
80 |
|
T34 |
10 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
5473823 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
auto[1] |
1251579 |
1 |
|
|
T28 |
1 |
|
T29 |
62 |
|
T34 |
4 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4386698 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
auto[1] |
2338704 |
1 |
|
|
T28 |
27 |
|
T29 |
119 |
|
T34 |
6 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
542861 |
1 |
|
|
T28 |
18 |
|
T29 |
34 |
|
T34 |
2 |
auto[1] |
auto[0] |
auto[1] |
628464 |
1 |
|
|
T29 |
38 |
|
T34 |
4 |
|
T35 |
114 |
auto[1] |
auto[1] |
auto[0] |
544264 |
1 |
|
|
T28 |
8 |
|
T29 |
23 |
|
T35 |
12 |
auto[1] |
auto[1] |
auto[1] |
623115 |
1 |
|
|
T28 |
1 |
|
T29 |
24 |
|
T35 |
50 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4382020 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
auto[1] |
2343382 |
1 |
|
|
T28 |
10 |
|
T29 |
82 |
|
T34 |
12 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
5465111 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
auto[1] |
1260291 |
1 |
|
|
T28 |
4 |
|
T29 |
39 |
|
T34 |
7 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4371775 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
auto[1] |
2353627 |
1 |
|
|
T28 |
12 |
|
T29 |
84 |
|
T34 |
9 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
548431 |
1 |
|
|
T28 |
8 |
|
T29 |
36 |
|
T34 |
2 |
auto[1] |
auto[0] |
auto[1] |
637745 |
1 |
|
|
T28 |
4 |
|
T29 |
25 |
|
T34 |
3 |
auto[1] |
auto[1] |
auto[0] |
544905 |
1 |
|
|
T29 |
9 |
|
T35 |
11 |
|
T61 |
275 |
auto[1] |
auto[1] |
auto[1] |
622546 |
1 |
|
|
T29 |
14 |
|
T34 |
4 |
|
T35 |
39 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4383744 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
auto[1] |
2341658 |
1 |
|
|
T28 |
22 |
|
T29 |
97 |
|
T34 |
9 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
5465722 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
auto[1] |
1259680 |
1 |
|
|
T28 |
13 |
|
T29 |
44 |
|
T34 |
15 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4377039 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
auto[1] |
2348363 |
1 |
|
|
T28 |
21 |
|
T29 |
100 |
|
T34 |
20 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
549628 |
1 |
|
|
T28 |
8 |
|
T29 |
25 |
|
T34 |
5 |
auto[1] |
auto[0] |
auto[1] |
631545 |
1 |
|
|
T28 |
7 |
|
T29 |
21 |
|
T34 |
15 |
auto[1] |
auto[1] |
auto[0] |
539055 |
1 |
|
|
T29 |
31 |
|
T35 |
9 |
|
T61 |
236 |
auto[1] |
auto[1] |
auto[1] |
628135 |
1 |
|
|
T28 |
6 |
|
T29 |
23 |
|
T35 |
63 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4383927 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
auto[1] |
2341475 |
1 |
|
|
T28 |
23 |
|
T29 |
102 |
|
T34 |
18 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
5467617 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
auto[1] |
1257785 |
1 |
|
|
T28 |
15 |
|
T29 |
24 |
|
T34 |
11 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4379182 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
auto[1] |
2346220 |
1 |
|
|
T28 |
20 |
|
T29 |
82 |
|
T34 |
19 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
545595 |
1 |
|
|
T28 |
3 |
|
T29 |
38 |
|
T34 |
6 |
auto[1] |
auto[0] |
auto[1] |
631458 |
1 |
|
|
T28 |
9 |
|
T29 |
21 |
|
T34 |
8 |
auto[1] |
auto[1] |
auto[0] |
542840 |
1 |
|
|
T28 |
2 |
|
T29 |
20 |
|
T34 |
2 |
auto[1] |
auto[1] |
auto[1] |
626327 |
1 |
|
|
T28 |
6 |
|
T29 |
3 |
|
T34 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4381147 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
auto[1] |
2344255 |
1 |
|
|
T28 |
16 |
|
T29 |
160 |
|
T34 |
9 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
5465091 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
auto[1] |
1260311 |
1 |
|
|
T28 |
13 |
|
T29 |
54 |
|
T34 |
12 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4372698 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
auto[1] |
2352704 |
1 |
|
|
T28 |
21 |
|
T29 |
76 |
|
T34 |
18 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
549389 |
1 |
|
|
T28 |
8 |
|
T29 |
16 |
|
T34 |
6 |
auto[1] |
auto[0] |
auto[1] |
632351 |
1 |
|
|
T28 |
13 |
|
T29 |
17 |
|
T34 |
9 |
auto[1] |
auto[1] |
auto[0] |
543004 |
1 |
|
|
T29 |
6 |
|
T35 |
6 |
|
T61 |
197 |
auto[1] |
auto[1] |
auto[1] |
627960 |
1 |
|
|
T29 |
37 |
|
T34 |
3 |
|
T35 |
30 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4375247 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
auto[1] |
2350155 |
1 |
|
|
T28 |
21 |
|
T29 |
147 |
|
T34 |
13 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
5473260 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
auto[1] |
1252142 |
1 |
|
|
T28 |
12 |
|
T29 |
61 |
|
T34 |
8 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4383934 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
auto[1] |
2341468 |
1 |
|
|
T28 |
21 |
|
T29 |
111 |
|
T34 |
17 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
547086 |
1 |
|
|
T28 |
3 |
|
T29 |
34 |
|
T34 |
9 |
auto[1] |
auto[0] |
auto[1] |
631250 |
1 |
|
|
T28 |
8 |
|
T29 |
18 |
|
T34 |
4 |
auto[1] |
auto[1] |
auto[0] |
542240 |
1 |
|
|
T28 |
6 |
|
T29 |
16 |
|
T35 |
56 |
auto[1] |
auto[1] |
auto[1] |
620892 |
1 |
|
|
T28 |
4 |
|
T29 |
43 |
|
T34 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4393336 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
auto[1] |
2332066 |
1 |
|
|
T28 |
29 |
|
T29 |
63 |
|
T34 |
22 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
5470702 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
auto[1] |
1254700 |
1 |
|
|
T28 |
23 |
|
T29 |
65 |
|
T35 |
167 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4383883 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
auto[1] |
2341519 |
1 |
|
|
T28 |
31 |
|
T29 |
114 |
|
T34 |
7 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
547199 |
1 |
|
|
T28 |
7 |
|
T29 |
40 |
|
T34 |
3 |
auto[1] |
auto[0] |
auto[1] |
637095 |
1 |
|
|
T28 |
6 |
|
T29 |
44 |
|
T35 |
137 |
auto[1] |
auto[1] |
auto[0] |
539620 |
1 |
|
|
T28 |
1 |
|
T29 |
9 |
|
T34 |
4 |
auto[1] |
auto[1] |
auto[1] |
617605 |
1 |
|
|
T28 |
17 |
|
T29 |
21 |
|
T35 |
30 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4389823 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
auto[1] |
2335579 |
1 |
|
|
T28 |
15 |
|
T29 |
114 |
|
T34 |
4 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
5477090 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
auto[1] |
1248312 |
1 |
|
|
T28 |
9 |
|
T29 |
28 |
|
T34 |
8 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4393266 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
auto[1] |
2332136 |
1 |
|
|
T28 |
22 |
|
T29 |
64 |
|
T34 |
10 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
543050 |
1 |
|
|
T28 |
4 |
|
T29 |
23 |
|
T34 |
2 |
auto[1] |
auto[0] |
auto[1] |
628960 |
1 |
|
|
T28 |
9 |
|
T29 |
13 |
|
T34 |
8 |
auto[1] |
auto[1] |
auto[0] |
540774 |
1 |
|
|
T28 |
9 |
|
T29 |
13 |
|
T35 |
9 |
auto[1] |
auto[1] |
auto[1] |
619352 |
1 |
|
|
T29 |
15 |
|
T35 |
50 |
|
T61 |
258 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4376641 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
auto[1] |
2348761 |
1 |
|
|
T28 |
16 |
|
T29 |
64 |
|
T34 |
18 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
5467363 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
auto[1] |
1258039 |
1 |
|
|
T28 |
10 |
|
T29 |
27 |
|
T34 |
3 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4372194 |
1 |
|
|
T25 |
175 |
|
T26 |
138 |
|
T27 |
92 |
auto[1] |
2353208 |
1 |
|
|
T28 |
34 |
|
T29 |
65 |
|
T34 |
8 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
552488 |
1 |
|
|
T28 |
20 |
|
T29 |
22 |
|
T34 |
5 |
auto[1] |
auto[0] |
auto[1] |
632792 |
1 |
|
|
T28 |
4 |
|
T29 |
23 |
|
T34 |
3 |
auto[1] |
auto[1] |
auto[0] |
542681 |
1 |
|
|
T28 |
4 |
|
T29 |
16 |
|
T35 |
18 |
auto[1] |
auto[1] |
auto[1] |
625247 |
1 |
|
|
T28 |
6 |
|
T29 |
4 |
|
T35 |
66 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |